EDE1108AJBG-1 查看數據表（PDF） - Elpida Memory, Inc

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EDE1108AJBG-1

1G bits DDR2 SDRAM

Elpida Memory, Inc 

EDE1108AJBG-1, EDE1116AJBG-1

ODT AC Electrical Characteristics

Parameter

Symbol

min.

max.

Unit Notes

ODT turn-on delay

tAOND

2

2

tCK

ODT turn-on

tAON

tAC (min)

tAC (max) + 700

ps 1, 3

ODT turn-on (power-down mode)

tAONPD

tAC(min) + 2000 3tCK + tAC(max) + 1000 ps

ODT turn-off delay

tAOFD

2.5

2.5

tCK 5

ODT turn-off

tAOF

tAC(min)

tAC(max) + 600

ps 2, 4, 5

ODT turn-off (power-down mode)

tAOFPD

tAC(min) + 2000 2.5tCK + tAC(max) + 1000 ps

ODT to power-down entry latency

tANPD

4



tCK

ODT power-down exit latency

tAXPD

11



tCK

Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.

ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.

2. ODT turn off time min is when the device starts to turn off ODT resistance.

ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.

3. When the device is operated with input clock jitter, this parameter needs to be derated by the actual

tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.)

4. When the device is operated with input clock jitter, this parameter needs to be derated by

{−tJIT(duty) max. − tERR(6-10per) max. } and { −tJIT(duty) min. − tERR(6-10per) min. } of the actual input

clock.(output deratings are relative to the SDRAM input clock.)

For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per) min. = −272ps,

tERR(6-10per) max. = +293ps, tJIT(duty) min. = −106ps and tJIT(duty) max. = +94ps, then

tAOF min.(derated) = tAOF min. + { −tJIT(duty) max. − tERR(6-10per) max. } = −450ps + { −94ps − 293ps}

= −837ps and tAOF max.(derated) = tAOF max. + { −tJIT(duty) min. − tERR(6-10per) min. } = 1050ps +

{ 106ps + 272ps} = +1428ps.

5. For tAOFD of DDR2-1066Mbps, the 1/2 clock of nCK in the 2.5 × nCK assumes a tCH(avg), average input

clock high pulse width of 0.5 relative to tCK(avg). tAOF min. and tAOF max. should each be derated by

the same amount as the actual amount of tCH(avg) offset present at the DRAM input with respect to 0.5.

For example, if an input clock has a worst case tCH(avg) of 0.48, the tAOF min. should be derated by

subtracting 0.02 × tCK(avg) from it, whereas if an input clock has a worst case tCH(avg) of 0.52, the tAOF

max. should be derated by adding 0.02 × tCK(avg) to it. Therefore, we have;

tAOF min.(derated) = tAC min. − [0.5 − Min.(0.5, tCH(avg) min.)] × tCK(avg)

tAOF max.(derated) = tAC max. + 0.6 + [Max.(0.5, tCH(avg) max.) − 0.5] × tCK(avg)

or

tAOF min.(derated) = Min.(tAC min., tAC min. − [0.5 − tCH(avg) min.] × tCK(avg))

tAOF max.(derated) = 0.6 + Max.(tAC max., tAC max. + [tCH(avg) max. − 0.5] × tCK(avg))

where tCH(avg) min. and tCH(avg) max. are the minimum and maximum of tCH(avg) actually measured

at the DRAM input balls.

Data Sheet E1733E31 (Ver.3.1)

16

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