HI-6011 查看數據表（PDF） - Holt Integrated Circuits

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HI-6011

ARINC 429 Transmitter / Dual Receiver for 8-Bit Bus

Holt Integrated Circuits 

HI-6011

READ/WRITE OPERATIONS

Read/write operations to the HI-6011 are performed via 3 address pins, A2:0, and 8 data pins, D7:0. The chip select

pin, CS, must be held low during all read/write operations. A single byte read is enabled by pulling the RD pin low.

Subsequent byte reads are performed by cycling RD high and then low for each additional byte read. Similarly, byte

writes are enabled in the same way by pulling the WR pin low and cycling high and then low for each additional byte

write. Table 3 and Table 4 summarize the address pins state for each permissible read and write operation respectively.

Table 3.  Address pins A2:0 state for permissible read operations

Read to HI-6011: (CS = 0, RD = 0)

A2:0 Description

000 Read Interrupt Status Register. See Section “Interrupt Status Register”.

Read Receiver 1 data.

The 32-bit ARINC word is read using 4 successive reads over the 8-bit parallel bus, as outlined in Table

001 2. RD must be pulled low for the first byte read and then cycled high and low for subsequent byte reads.

CS should be held low during the entire 4-byte cycle.

If more than four reads are issued, the fifth re-reads the data originally read on the first read, etc.).

Read Receiver 2 data.

010

Same operation as Receiver 1 above.

011 Read Transmitter/General Status Register. See Section “Transmitter/General Status Register”.

1xx No function. Returns all zeros.

Table 4.  Address pins A2:0 state for permissible write operations

Write to HI-6011: (CS = 0, WR = 0)

A2:0 Description

Write Transmit FIFO.

The 32-bit ARINC word is written to the transmit FIFO using 4 successive writes over the 8-bit parallel

bus, as outlined in Table 2. WR must be pulled low for the first byte write and then cycled high and low

for subsequent byte writes. CS should be held low during the entire 4-byte cycle.

000

Bit 32 will be automatically overwritten with the correct parity.

Up to 5 32-bit words may be queued in the transmit FIFO. A minimum of 8μs must be allowed between

the last byte of each word (write cycle 4) and the first byte of the next word (write cycle 1). See Section

“Transmit FIFO Operation”.

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