HI-6011 查看數據表（PDF） - Holt Integrated Circuits

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HI-6011

ARINC 429 Transmitter / Dual Receiver for 8-Bit Bus

Holt Integrated Circuits 

HI-6011

TRANSMIT FIFO OPERATION

One Transmit channel is provided. Outputs are as follows:

Data

Idle

1

0

Asserted Output

LO

Pulses HI (RZ)

LO

Negated Output

LO

LO

Pulses HI (RZ)

A FIFO buffer allows five transmit words to be queued up while a preceding one is being serialized. These may be

written to the HI-6011 with a minimum of 8μs between the last byte write (fourth) of one word and the first byte write of

the next word. The interrupt is activated when the FIFO is full and no more transmit words can be written (any written

under this condition are ignored and thus, lost).

The Interrupt is also activated when the transmitter becomes empty, a condition when six words may be written to the

FIFO system.

To write a word to the transmitter, status should first be checked to determine if the FIFO can except data. Then four

consecutive writes are performed: the first is for bits 1-8, the second for bits 9-16, etc. Bit 1 is the first transmitted bit

in the serial stream followed sequentially by bit 2 through 32. Data written to the transmitter must be stable during the

trailing (rising) edge of WR.

The transmitter inserts the proper parity bit on transmitted words. Bit 32 written to the transmitter is ignored.

INTERRUPTS

Two low true interrupts (RINT and XINT) are provided on separate output pins. These are open drain outputs which

may be “wire OR’d” together. Each pin is capable of sinking 4mA.

RINT is pulsed LOW (‘0’) for 2μs by either of the following conditions:

1. Receiver 1 has received a word – INT status retained until explicitly reset or until another word is received

in mode 0.

2. Receiver 2 has received a word – INT status retained until explicitly reset or until another word is received

in mode 0.

XINT is pulsed low for 2μs by either of the following conditions:

1. Transmitter FIFO and serializer completely empty (6 words may be written to it).

2. Transmitter buffer is full.

RINT and XINT are intended for use as edge activated signals. The Interrupt Status Register must be read to determine

the source of the interrupts.

A reset (hardware or software) will not cause a XINT for transmitter empty. The controller should know this transmitter

status exists by virtue of intentionally issuing such a reset.

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