HT48CA5 查看數據表（PDF） - Holtek Semiconductor

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HT48CA5

Remote Type 8-Bit MCU

Holtek Semiconductor 

HT48RA5/HT48CA5

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake up the

device by mask option. Awakening from an I/O port stim-

ulus, the program will resume execution of the next in-

struction. If it awakens from an interrupt, two sequence

may occur. If the related interrupt is disabled or the inter-

rupt is enabled but the stack is full, the program will re-

sume execution at the next instruction. If the interrupt is

enabled and the stack is not full, the regular interrupt re-

sponse takes place. If an interrupt request flag is set to

²1² before entering the HALT mode, the wake-up func-

tion of the related interrupt will be disabled. Once a

wake-up event occurs, it takes 1024 tSYS (system clock

period) to resume normal operation. In other words, a

dummy period will be inserted after a wake-up. If the

wake-up results from an interrupt acknowledge signal,

the actual interrupt subroutine execution will be delayed

by one or more cycles. If the wake-up results in the next

instruction execution, this will be executed immediately

after the dummy period is finished.

To minimize power consumption, all the I/O pins should

be carefully managed before entering the HALT status.

Reset

There are three ways in which a reset can occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a ²warm re -

set² that resets only the program counter and SP, leav-

ing the other circuits in their original state. Some regis-

ters remain unchanged during other reset conditions.

Most registers are reset to the ²initial condition² when

the reset conditions are met. By examining the PDF and

TO flags, the program can distinguish between different

²chip resets².

TO PDF

RESET Conditions

0 0 RES reset during power-up

u u RES reset during normal operation

0 1 RES wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT wake-up HALT

Note: ²u² stands for unchanged

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem reset (power-up, WDT time-out or RES reset) or the

system awakes from the HALT state.

When a system reset occurs, the SST delay is added

during the reset period. Any wake-up from HALT will en-

able the SST delay.

The functional unit chip reset status are shown below.

Program Counter

Interrupt

Prescaler

WDT

Timer/event Counter

Input/output Ports

Stack Pointer

000H

Disable

Clear

Clear. After master reset,

WDT begins counting

Off

Input mode

Points to the top of the stack

VDD

RES

tS S T

S S T T im e - o u t

C h ip R e s e t

Reset Timing Chart

V DD

100kW

0 .1 m F

RES

B a s ic

R eset

C ir c u it

V DD

0 .0 1 m F

100kW

10kW

0 .1 m F

RES

H i-n o is e

R eset

C ir c u it

Reset Circuit

Note:

Most applications can use the Basic Reset Cir-

cuit as shown, however for applications with ex-

tensive noise, it is recommended to use the

Hi-noise Reset Circuit.

H A LT

W DT

W a rm R e s e t

RES

O SC1

SST

1 0 - b it R ip p le

C o u n te r

C o ld

R eset

S y s te m R e s e t

Reset Configuration

Rev. 1.40

12

May 22, 2009

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