IDT72V3611 查看數據表（PDF） - Integrated Device Technology

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IDT72V3611

3.3 VOLT CMOS SyncFIFO 64 x 36

Integrated Device Technology 

IDT72V3611 3.3V, CMOS SyncFIFOTM

64 x 36

CLKB

CSB

tCLK

tCLKH

tCLKL

LOW

W/RB LOW

MBB LOW

tENS2

ENB

tENH2

COMMERCIAL TEMPERATURE RANGE

EFB

B0 -B35

HIGH

tA

Previous Word in FIFO Output Register

tSKEW1(1)

CLKA

tCLK

tCLKH

tCLKL

1

FF

CSA LOW

FIFO Full

Next Word From FIFO

2

tWFF

tWFF

WRA HIGH

tENS3

tENH3

MBA

ENA

tENS2

tDS

tENH2

tDH

A0 - A35

To FIFO

4657 drw 09

NOTE:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising

CLKA edge is less than tSKEW1, then the transition of FF HIGH may occur one CLKA cycle later than shown.

Figure 6. FF Flag Timing and First Available Write when the FIFO is Full

CLKA

ENA

tENS2

tENH2

CLKB

AE

tSKEW2(1)

1

X Word in FIFO

2

tPAE

(X+1) Words in FIFO

tENS2

tPAE

tENH2

ENB

4657 drw 10

NOTES:

1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and

rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.

2. FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L).

Figure 7. Timing for AE when the FIFO is Almost-Empty

15

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