IDT72V3611 查看數據表（PDF） - Integrated Device Technology

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IDT72V3611

3.3 VOLT CMOS SyncFIFO 64 x 36

Integrated Device Technology 

IDT72V3611 3.3V, CMOS SyncFIFOTM

64 x 36

CLKB

CSB

W/RB

MBB

ENB

B0 - B35

tENS1

tENS1

tENS1

tENS1

tDS

W1

tENH1

tENH1

tENH1

tENH1

tDH

COMMERCIAL TEMPERATURE RANGE

CLKA

MBF2

CSA

W/RA

MBA

ENA

tEN

A0 - A35

NOTE:

1. Port-A parity generation off (PGA = L)

tPMF

tPMF

tENS2

tENH2

tPMR

tDIS

W1 (Remains valid in Mail2 Register after read)

4657 drw 13

Figure 10. Timing for Mail2 Register and MBF2 Flag

ODD/

EVEN

W/RA

MBA

PGA

PEFA

Valid

NOTE:

1. CSA = L and ENA = H.

tPOPE

Valid

tPOPE

Valid

tPEPE

Figure 11. ODD/EVEN, W/RA, MBA, and PGA to PEFA Timing

tPEPE

Valid

4657 drw 14

ODD/

EVEN

W/RB

MBB

PGB

PEFB

Valid

NOTE:

1. CSB = L and ENB = H.

tPOPE

Valid

tPOPE

Valid

tPEPE

Figure 12. ODD/EVEN, W/RB, MBB, and PGB to PEFB Timing

17

tPEPE

Valid

4657 drw 15

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