IDT72V3611 查看數據表（PDF） - Integrated Device Technology

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IDT72V3611

3.3 VOLT CMOS SyncFIFO 64 x 36

Integrated Device Technology 

IDT72V3611 3.3V, CMOS SyncFIFOTM

64 x 36

COMMERCIAL TEMPERATURE RANGE

ODD/

EVEN

CSA

LOW

W/RA

MBA

PGA

A8, A17,

A26, A35

NOTE:

1. ENA = H.

tEN

tPEPB

tPOPB

tPEPB

Mail2 Data

Generated Parity

Generated Parity

Figure 13. Parity Generation Timing when reading from the Mail2 Register

Mail2 Data

4657 drw 16

ODD/

EVEN

CSB

LOW

W/RB

MBB

PGB

B8, B17,

B26, B35

NOTE:

1. ENB = H.

tPEPB

tEN

tMDV

tPOPB

tPEPB

Generated Parity

Generated Parity

Mail1

Data

Figure 14. Parity Generation Timing when reading from the Mail1 Register

Mail1 Data

4657 drw 17

18

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