74F1763 查看數據表（PDF） - Philips Electronics

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74F1763

Intelligent DRAM controller (IDC)

Philips Electronics 

Philips Semiconductors

Intelligent DRAM controller (IDC)

Product specification

74F1763

TIMING DIAGRAMS (Continued)

CP

8

9

7

REQ

11

10

GNT

ALE

12

RA0–9,

CA0–9

ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ1VA3ÇÇADLDIDREÇÇ1S4S ÇÇÇÇÇÇÇÇÇÇÇÇNOÇÇTE1 ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ

15

HLDROW = 0

16

HLDROW = 1

MA0–9

REFRESH

ADDRESS

REFRESH

ADDRESS

NOTE 2 VALID ROW ADDRESS

VALID COLUMN ADDRESS

PRECHRG = 0 PRECHRG = 1

RAS

18

17

19

21

22

20

36

35

23

25

24

PAGE = 1

26

CAS

PAGE

DTACK

3-STATE

28

ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ27ÇÇÇNOTEÇÇÇ3 ÇÇÇÇÇÇ 29

30

31

32

3-STATE

NOTE 1: If the RA0–9 and CA0–9 address inputs are not latched, RA0–9 inputs should remain valid until row address hold time is met and CA0–9 inputs should remain valid until column

address hold time is met.

NOTE 2: MA0–9 outputs will contain the present row address on the RA0–RA9 inputs or the last row address latched into the device.

NOTE 3: PAGE input may be asserted anytime before this rising clock edge in order to hold RAS low.

SF01406

Figure 4. Memory access cycle timing following a refresh cycle

1999 Jan 08

11

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