L6566BH 查看數據表（PDF） - STMicroelectronics

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产品描述 (功能)

生产厂家

L6566BH

Multimode controller for SMPS

STMicroelectronics 

L6566BH

Application information

Ideally, the voltage generated by the self-supply winding and the output voltage should be

given by the relation between the Naux/Ns turn ratio only. Actually, numerous non-idealities,

mainly transformer parasites, cause the actual ratio to deviate from the ideal one. Line

regulation is quite good, in the range of ± 2%, whereas load regulation is about ± 5% and

output voltage tolerance is in the range of ± 10%.

The dynamics of the pin are in the 2.5 to 5 V range. The voltage at the pin is clamped

downwards at about 2 V. If the clamp is externally overridden and the voltage on the pin is

pulled below 1.4 V, the L6566BH shuts down. This condition is latched as long as the device

is supplied. While the device is disabled, however, no energy is coming from the self-supply

circuit, therefore the voltage on the Vcc capacitor decays and crosses the UVLO threshold

after some time, which clears the latch and lets the HV generator restart. This function is

intended for an externally controlled burst-mode operation at light load with a reduced

output voltage, a technique typically used in multi-output SMPS, such as those for TVs or

monitors (see the timing diagram Figure 15).

Figure 15. Externally controlled burst-mode operation by driving the COMP pin:

timing diagram

Vcc

(pin 5)

VccON

VccOFF

Vccrestart

Standby is commanded here

COMP

t

(pin 9)

GD

(pin 4)

Vcc_OK

Icharge

0.85 mA

Vout

t

t

t

t

t

AM11491v1

5.6

PWM comparator, PWM latch and voltage feedforward blocks

The PWM comparator senses the voltage across the current sense resistor Rs and, by

comparing it to the programming signal delivered by the feedforward block, determines the

exact time when the external MOSFET is to be switched off. Its output resets the PWM

latch, previously set by the oscillator or the ZCD triggering block, which asserts the gate

driver output low. The use of PWM latch avoids spurious switching of the MOSFET that may

result from the noise generated (“double-pulse suppression”).

Doc ID 16610 Rev 2

25/51

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