LFECP20E-5F900C 查看數據表（PDF） - Lattice Semiconductor

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LFECP20E-5F900C

LatticeECP/EC Family Data Sheet Introduction

Lattice Semiconductor 

Lattice Semiconductor

Architecture

LatticeECP/EC Family Data Sheet

Table 2-5. PLL Signal Descriptions

Signal

CLKI

CLKFB

RST

CLKOS

CLKOP

CLKOK

LOCK

DDAMODE

DDAIZR

DDAILAG

DDAIDEL[2:0]

DDAOZR

DDAOLAG

DDAODEL[2:0]

I/O

Description

I

Clock input from external pin or routing

I

PLL feedback input from CLKOP, clocknet, or external pin

I

“1” to reset PLL

O PLL output clock to clock tree (phase shifted/duty cycle changed)

O PLL output clock to clock tree (No phase shift)

O PLL output to clock tree through secondary clock divider

O “1” indicates PLL LOCK to CLKI

I

Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static)

I

Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on

I

Dynamic Delay Lag/Lead. “1”: Lead, “0”: Lag

I

Dynamic Delay Input

O Dynamic Delay Zero Output

O Dynamic Delay Lag/Lead Output

O Dynamic Delay Output

For more information on the PLL, please see details of additional technical documentation at the end of this data

sheet.

Dynamic Clock Select (DCS)

The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and

outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is

toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-13 illustrates

the DCS Block Macro.

Figure 2-13. DCS Block Primitive

CLK0

CLK1

SEL

DCS

DCSOUT

Figure 2-14 shows timing waveforms of the default DCS operating mode. The DCS block can be programmed to

other modes. For more information on the DCS, please see details of additional technical documentation at the end

of this data sheet.

2-11

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