LFECP20E-5F900C 查看數據表（PDF） - Lattice Semiconductor
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LFECP20E-5F900C Datasheet PDF : 117 Pages
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Lattice Semiconductor
Architecture
LatticeECP/EC Family Data Sheet
MULT sysDSP Element
This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,
are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.
Figure 2-18 shows the MULT sysDSP element.
Figure 2-18. MULT sysDSP Element
Shift Register B In
Shift Register A In
Multiplicand
m
m
Multiplier
n
n
n
Input Data
Register B
n
m
Input Data
m
Register A
n
m
Multiplier
x
m+n
(default)
Pipeline
Register
m+n
Output
Signed
Input
Register
To
Multiplier
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Shift Register B Out
Shift Register A Out
MAC sysDSP Element
In this case the two operands, A and B, are multiplied and the result is added with the previous accumulated value.
This accumulated value is available at the output. The user can enable the input and pipeline registers but the out-
put register is always enabled. The output register is used to store the accumulated value. A registered overflow
signal is also available. The overflow conditions are provided later in this document. Figure 2-19 shows the MAC
sysDSP element.
Figure 2-19. MAC sysDSP Element
Shift Register B In
Shift Register A In
Multiplicand
Multiplier
SignedAB
Addn
Accumsload
m
m
n
n
n
m
Input Data
m
Register A
Input Data
Register B
n
Input
Register
Input
Register
Input
Register
n
n
Pipeline
Register
Pipeline
Register
Pipeline
Register
Multiplier
x m+n
(default)
Pipeline
Register
To
Accumulator
To
Accumulator
To
Accumulator
Shift Register B Out
Shift Register A Out
Accumulator
m+n+16 bits
(default)
m+n+16 bits
(default)
Output
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Overflow
signal
2-16
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