LTC2246LX(RevB) 查看數據表（PDF） - Linear Technology

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LTC2246LX
(Rev.:RevB)

14-Bit, 25Msps 125°C ADC In LQFP

Linear Technology 

LTC2246H

APPLICATIONS INFORMATION

DAC to produce a residue. The residue is amplified and

output by the residue amplifier. Successive stages operate

out of phase so that when the odd stages are outputting

their residue, the even stages are acquiring that residue

and vice versa.

When CLK is low, the analog input is sampled differentially

directly onto the input sample-and-hold capacitors, inside

the “Input S/H” shown in the block diagram. At the instant

that CLK transitions from low to high, the sampled input is

held. While CLK is high, the held input voltage is buffered

by the S/H amplifier which drives the first pipelined ADC

stage. The first stage acquires the output of the S/H dur-

ing this high phase of CLK. When CLK goes back low, the

first stage produces its residue which is acquired by the

second stage. At the same time, the input S/H goes back to

acquiring the analog input. When CLK goes back high, the

second stage produces its residue which is acquired by the

third stage. An identical process is repeated for the third,

fourth and fifth stages, resulting in a fifth stage residue

that is sent to the sixth stage ADC for final evaluation.

Each ADC stage following the first has additional range to

accommodate flash and amplifier offset errors. Results

from all of the ADC stages are digitally synchronized such

that the results can be properly combined in the correction

logic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2246H

CMOS differential sample-and-hold. The analog inputs are

connected to the sampling capacitors (CSAMPLE) through

NMOS transistors. The capacitors shown attached to

each input (CPARASITIC) are the summation of all other

capacitance associated with each input.

During the sample phase when CLK is low, the transistors

connect the analog inputs to the sampling capacitors and

they charge to and track the differential input voltage. When

CLK transitions from low to high, the sampled input voltage

is held on the sampling capacitors. During the hold phase

when CLK is high, the sampling capacitors are disconnected

from the input and the held voltage is passed to the ADC

core for processing. As CLK transitions from high to low,

LTC2246H

VDD

15Ω

AIN+

VDD

15Ω

AIN–

CPARASITIC

1pF

CPARASITIC

1pF

CSAMPLE

4pF

CSAMPLE

4pF

CLK

2246H F02

Figure 2. Equivalent Input Circuit

the inputs are reconnected to the sampling capacitors to

acquire a new sample. Since the sampling capacitors still

hold the previous sample, a charging glitch proportional

to the change in voltage between samples will be seen

at this time. If the change between the last sample and

the new sample is small, the charging glitch seen at the

input will be small. If the input change is large, such as

the change seen with input frequencies near Nyquist, then

a larger charging glitch will be seen.

Single-Ended Input

For cost sensitive applications, the analog inputs can be

driven single-ended. With a single-ended input the har-

monic distortion and INL will degrade, but the SNR and

DNL will remain unchanged. For a single-ended input, AIN+

should be driven with the input signal and AIN– should

be connected to VCM or a low noise reference voltage

between 1V and 1.5V.

Common Mode Bias

For optimal performance the analog inputs should be driven

differentially. Each input should swing ±0.5V for the 2V

range or ±0.25V for the 1V range, around a common mode

voltage of 1.5V. The VCM output pins (Pins 44, 45) may be

used to provide the common mode bias level. VCM can be

tied directly to the center tap of a transformer to set the DC

input level or as a reference level to an op amp differential

driver circuit. The VCM pins must be bypassed to ground

close to the ADC with a 2.2μF or greater capacitor.

2246hfb

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