MSM6242B 查看數據表（PDF） - Oki Electric Industry

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MSM6242B

DIRECT BUS CONNECTED CMOS REAL TIME CLOCK/CALENDAR

Oki Electric Industry 

MSM6242B

¡ Semiconductor

START

START

30-SECOND

ADJ BIT = 1

30-SECOND

ADJ BIT = 1

READ 30-SECOND

ADJ BIT

NO

125µs PASS?

30-SECOND

NO

ADJ BIT = 0?

YES

END

YES

(B)

END

(A)

Figure 11. Writing 30-Second Adj. bit (Two Ways A, B)

CE REGISTER (Control E Register)

a) MASK (D0) –

b) ITRPT/STND (D1) –

c) T0 (D2), T1 (D3) –

This bit controls the STD.P output. When MASK = 1, then STD.P

= 1 (open); when MASK = 0, then STD.P = output mode. The

relationship between the MASK bit and STD.P output is shown

Figure 12.

The ITRPT/STND input is used to switch the STD.P output

between its two modes of operation, interrupt and Standard

timing waveforms. When ITRPT/STND = 0 a fixed cycle wave-

form with a low-level pulse width of 7.8125ms is present at the

STD.P output. At this time the MASK bit must equal 0, while the

period in either mode is determined by T0 (D2) and T1 (D3) of

Register E.

These two bits determine the period of the STD.P output in both

interrupt and Fixed timing waveform modes. The tables below

show the timing associated with the T0, T1 inputs as well as their

relationship to INTRPT/STND and STD.P.

"1"

MASK BIT "0"

"1"

"INTERRUPT" DOES

NOT OCCUR BECAUSE

"0"

MASK BIT IS "1"

MASK BIT

STD.P OUTPUT

OPEN

LOW LEVEL

"INTERRUPT" TIMING

WRITE "0" INTO IRQ FLAG BIT

INTRT/STND BIT = "1"

STD.P

OUTPUT

Figure 12.

"1"

"1"

OUTPUT DOES NOT OCCUR

AT LOW LEVEL BECAUSE

"0"

"0"

MASK BIT IS "1"

INTRT/STND BIT = "0"

OPEN

LOW LEVEL

OUTPUT TIMING

AUTOMATIC RETURN

t1

t0

0

0

0

1

1

0

1

1

34

TABLE 2

Period

1/64 second

1 second

1 minute

1 hour

Duty CYCLE of "0" level when

ITRPT/STND bit is "0".

1/2

1/128

1/7680

1/460800

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