MSM6242B 查看數據表（PDF） - Oki Electric Industry
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MSM6242B Datasheet PDF : 18 Pages
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MSM6242B
¡ Semiconductor
TYPICAL APPLICATION INTERFACE WITH MSM6242B AND
MICROCONTROLLERS
8085
AD3
AD2
AD1
AD0
A8 ~ A15
S1
S0
IO/M
ALE
RD
WR
MSM6242B
D3
D2
D1
D0
A3
A2
A1
A0
CS0
ALE
R1
RD
R2
WR
8085
A/D
A8 ~ A12
A8 ~ A15
S1
S0
IO/M
RD
WR
MSM6242B
D3
D2
D1
D0
A3
A2
A1
A0
CS0
ALE
R1
RD
R2
WR
MEMORY MAPPED
I/O MAPPED
Note : If 8085 does not enter into the state of HALT or HOLD during CS1 = "H" of
MSM6242B, R1 and R2 are not required.
Figure 15.
Z80
MSM6242B
D3
D3
D2
D2
D1
D1
D0
D0
A3
A3
A2
A2
A1
A1
A0
DECODER
A0
A4 ~ A15
IORQ
MREQ
RD
WR
VDD CS0
ALE
G1
RD
WR
G2
Note : It depends upon the switching
characterisrics decided by a X'tal used
for a Z80 that either of IORQ and MREQ
is used.
Figure 16.
MCS48
BUS3
BUS2
BUS1
BUS0
BUS 4-7
ALE
RD
WR
DECODER
MSM6242B
D3
D2
D1
D0
A3
A2
A1
A0
CS0
ALE
RD
WR
Figure 17.
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