MAX17006BETP 查看數據表（PDF） - Maxim Integrated

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MAX17006BETP

1.2MHz, Low-Cost, High-Performance Chargers

Maxim Integrated 

1.2MHz, Low-Cost,

High-Performance Chargers

MOSFET Drivers

The DHI and DLO outputs are optimized for driving

moderate-sized power MOSFETs. The MOSFET drive

capability is the same for both the low-side and high-

sides switches. This is consistent with the variable duty

factor that occurs in the notebook computer environ-

ment where the battery voltage changes over a wide

range. There must be a low-resistance, low-inductance

path from the DLO driver to the MOSFET gate to pre-

vent shoot-through. Otherwise, the sense circuitry in the

MAX17005B/MAX17006B interprets the MOSFET gate

as off while there is still charge left on the gate. Use

very short, wide traces measuring 10 to 20 squares or

fewer (1.25mm to 2.5mm wide if the MOSFET is 25mm

from the device).

The high-side driver (DHI) swings from LX to 5V above

LX (BST) and has a typical impedance of 1.5Ω sourc-

ing and 0.8Ω sinking. The strong high-side MOSFET

driver eliminates most of the power dissipation due to

switching losses. The low-side driver (DLO) swings

from LDO to ground and has a typical impedance of 3Ω

sinking and 3Ω sourcing. This helps prevent DLO from

being pulled up when the high-side switch turns on due

to capacitive coupling from the drain to the gate of the

low-side MOSFET. This places some restrictions on the

MOSFETs that can be used. Using a low-side

MOSFET with smaller gate-to-drain capacitance can

prevent these problems.

Design Procedure

MOSFET Selection

Choose the n-channel MOSFETs according to the maxi-

mum required charge current. The MOSFETs must be

able to dissipate the resistive losses plus the switching

losses at both VDCIN(MIN) and VDCIN(MAX).

For the high-side MOSFET, the worst-case resistive

power losses occur at the maximum battery voltage

and minimum supply voltage:

PDCOND (High Side)

=

VBATT(MAX)

VDCIN(MIN)

× ICHG2

× RDS(ON)

Generally, a low gate-charge high-side MOSFET is pre-

ferred to minimize switching losses. However, the

RDS(ON) required to stay within package power dissi-

pation often limits how small the MOSFET can be. The

optimum occurs when the switching losses equal the

conduction losses. High-side switching losses do not

usually become an issue until the input is greater than

approximately 15V. Calculating the power dissipation in

N1 due to switching losses is difficult since it must

allow for difficult quantifying factors that influence the

turn-on and turn-off times. These factors include the

internal gate resistance, gate charge, threshold volt-

age, source inductance, and PCB layout characteris-

tics. The following switching-loss calculation provides

only a very rough estimate and is no substitute for

breadboard evaluation, preferably including a verifica-

tion using a thermocouple mounted on N1:

PDSW (HS)

=

1

2

×

tTRANS

×

VCSSP

×

ICHG

×

fSW

where tTRANS is the drivers transition time and can be

calculated as follows:

( ) tTRANS

=

⎛1

⎝⎜ IGSRC

+

1

IGSNK

⎞

⎠⎟

×

QGD + QGS

IGSRC and IGSNK are the peak gate-drive source/sink

current (3Ω sourcing and 0.8Ω sinking, typically). The

MAX17005B/MAX17006B/MAX17015B control the

switching frequency as shown in the Typical Operating

Characteristics.

The following is the power dissipated due to the high-

side n-channel MOSFET’s output capacitance (CRSS):

PDCRSS (HS)

≈

V2CSSP

×

CRSS

2

×

fSW

The following high-side MOSFET’s loss is due to the

reverse-recovery charge of the low-side MOSFET’s

body diode:

PDQRR (HS)

=

QRR2

×

VCSSP

2

×

fSW

Ignore PDQRR(HS) if a Schottky diode is used parallel

to a low-side MOSFET.

The total high-side MOSFET power dissipation is:

PDTOTAL (HS) ≈ PDCOND(HS) + PDSW (HS)

+ PDCRSS (HS) + PDQRR(HS)

Switching losses in the high-side MOSFET can become

an insidious heat problem when maximum AC adapter

voltages are applied. If the high-side MOSFET chosen

for adequate RDS(ON) at low-battery voltages becomes

hot when biased from VDCIN(MAX), consider choosing

another MOSFET with lower parasitic capacitance.

For the low-side MOSFET (N2), the worst-case power

dissipation always occurs at the maximum input voltage:

PDCOND(LS)

=

⎛

⎜1-

⎝

VBATT(MIN)

VCSSP(MAX)

⎞

⎟

⎠

×

ICHG2

×

RDS(ON)

______________________________________________________________________________________ 17

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