MB1507 查看數據表（PDF） - Fujitsu

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MB1507

SERIAL INPUT PLL FREQUENCY SYNTHESIZER

Fujitsu 

MB1507

t1, t2, t3, t4, t5≥1µs

Data S19=MSB S18

*(SW) (S14)

Clock

SERIAL DATA INPUT TIMING

S11 S10

(S7)

(S6)

S1=LSB

(S1)

C: CONTROL BIT

(C: CONTROL BIT)

LE

t1

t2

t3

t4

t5

NOTES: Parenthesis data is used for setting divide ratio of programmable reference divider.

On rising edge of clock shifts one bit of data into the shift register.

PHASE CHARACTERISTICS

VCO POLARITY

FC pin is provided to change phase polarity of phase comparator. Characteris-

tics of internal charge pump output level (DO), phase comparator output level

(ØR, ØP) are reversed depending upon FC pin input level. Also, monitor pin

(fout) output level of phase comparator is controlled by FC pin input level.

1

FC=H or open

FC=L

DO ØR ØP fout DO ØR ØP fout

fr>fp

H L L (fr) L H Z (fp)

fr=fp

Z L Z (fr) Z L Z (fp)

fr<fp

L H Z (fr) H L L (fp)

Note: Z=(High impedance)

Depending upon VCO polarity, FC pin should be set accordingly:

When VCO polarity are like 1 , FC should be set High or open circuit;

When VCO polarity are like 2 , FC should be set Low.

2

VCO INPUT VOLTAGE

6

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