MB95FV100D-103PBT 查看數據表（PDF） - Fujitsu
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MB95FV100D-103PBT Datasheet PDF : 74 Pages
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MB95160M Series
■ BLOCK DIAGRAM
RST
X0/X1
X0A/X1A
P00/INT00 to
P07/INT07
P10/UI0
P11/UO0
P12/UCK0
P13/TRG0/ADTG
P14/PPG0
P20/PPG00
P21/PPG01
P22/TO00
P23/TO01/SCL0
P24/EC0/SDA0
(P00/AN00 to
P07/AN07)
AVCC
AVSS
AVR
F2MC-8FX CPU
Reset control
Clock control
Watch prescaler
Watch counter
External interrupt
ROM
RAM
Interrupt control
Wild register
8/16-bit PPG ch.1
UART/SIO
16-bit PPG
8/16-bit PPG ch.0
8/16-bit
compound timer ch.1
LIN-UART
8/16-bit
compound timer ch.0
I2C
LCDC
8/10-bit
A/D converter
Port
Port
Other pins
MOD, VSS, VCC, C
P60/SEG16/PPG10
P61/SEG17/PPG11
P62/SEG18/TO10
P63/SEG19/TO11
P64/SEG20/EC1
P65/SEG21/SCK
P66/SEG22/SOT
P67/SEG23/SIN
P90/V3 to P93/V0
PA0/COM0 to PA3/COM3
PB0/SEG00 to PB7/SEG07
PC0/SEG08 to PC7/SEG15
(P00/SEG31 to P07/SEG24)
P94/P95
17
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