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33981 查看數據表(PDF) - Freescale Semiconductor

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33981 Datasheet PDF : 40 Pages
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FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33981 is a high-frequency self-protected silicon
4.0 mRDS(ON) high side switch used to replace
electromechanical relays, fuses, and discrete devices in
power management applications. The 33981 can be
controlled by pulse-width modulation (PWM) with a frequency
up to 60 kHz. It is designed for harsh environments, and it
includes self-recovery features.
The 33981 is suitable for loads with high inrush current, as
well as motors and all types of resistive and inductive loads.
A dedicated parallel input is available for an external low side
control with protection features and cross-conduction
management.
FUNCTIONAL PIN DESCRIPTIONS
OUTPUT CURRENT MONITORING (CSNS)
This pin is used to output a current proportional to the high
side OUT current and is used externally to generate a
ground-referenced voltage for the microcontroller (MCU) to
monitor OUT current.
TEMPERATURE FEEDBACK (TEMP)
This pin reports an analog value proportional to the
temperature of the GND flag (pin 13). It is used by the MCU
to monitor board temperature.
ENABLE [ACTIVE HIGH] (EN)
This is an input used to place the device in a low-current
Sleep Mode. This pin has an active passive internal pull-
down.
INPUT HIGH SIDE (INHS)
The input pin is used to directly control the OUT. This input
has an active internal pull-down current source and requires
CMOS logic levels.
FAULT STATUS (FS)
This pin is an open drain-configured output requiring an
external pull-up resistor to VDD (5.0 V) for fault reporting.
When a device fault condition is detected, this pin is active
LOW.
INPUT LOW SIDE (INLS)
This input pin is used to directly control an external low
side N-channel MOSFET and has an active internal pull-
down current source and requires CMOS logic levels. It can
be controlled independently of the INHS depending of CONF
pin.
CONFIGURATION INPUT (CONF)
This input pin is used to manage the cross-conduction
between the internal high side N-channel MOSFET and the
external low side N-channel MOSFET. The pin has an active
internal pull-up current source. When CONF is at 0 V, the
two MOSFETs are controlled independently. When CONF is
at VDD 5.0 V, the two MOSFETs cannot be on at the same
time.
LOW SIDE OVERLOAD (OCLS)
This pin sets the VDS protection level of the external low
side MOSFET. This pin has an active internal pull-up current
source. It must be connected to an external resistor.
DRAIN LOW SIDE (DLS)
This pin is the drain of the external low side N-channel
MOSFET. Its monitoring allows protection features: low side
short protection and VPWR short protection.
LOW SIDE GATE (GLS)
This pin is an output used to drive the gate of the external
low side N-channel MOSFET.
SLEW RATE CONTROL (SR)
A capacitor connected between this pin and ground is
used to control the output slew rate.
BOOTSTRAP CAPACITOR (CBOOT)
A capacitor connected between this pin and OUT is used
to switch the OUT in PWM mode.
GROUND (GND)
This pin is the ground for the logic and analog circuitry of
the device.
POSITIVE POWER SUPPLY (VPWR)
This pin connects to the positive power supply and is the
source input of operational power for the device. The VPWR
pin is a backside surface mount tab of the package.
OUTPUT (OUT)
Protected high side power output to the load. Output pins
must be connected in parallel for operation.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33981
15

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