33981 查看數據表（PDF） - Freescale Semiconductor

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33981

Single High Side Switch (4.0 mOhm), PWM clock up to 60 kHz

Freescale Semiconductor 

FUNCTIONAL DEVICE OPERATION

PROTECTION AND DIAGNOSTIC FEATURES

directly but rather its effects on the low side MOSFET. When

VDLS > VOCLS, the GLS pin goes to 0 V and the OCLS

internal current source is disconnected and OCLS goes to

0 V. The GLS pin and the OCLS pin are reset (and the fault

is delatched) by a logic [0] at the INLS pin for at least

tRST(DIAG). Figure 13 and Figure 14 illustrate the behavior in

case of overload on the low side gate driver.

When connected to an external resistor, the OCLS pin with

its internal current source sets the VOCLS level. By changing

the external resistance, the protection level can be adjusted

depending on low side characteristics. A 33 k resistor gives

a VDS level of 3.3 V typical.

This protection circuitry measures the voltage between the

drain of the low side (DLS pin) and the 33981 ground (GND

pin). For this reason it is key that the low side source, the

33981 ground, and the external resistance ground

connection are connected together in order to prevent false

error detection due to ground shifts.

The maximum OCLS voltage being 4.0 V, a resistor bridge

on DLS must be used to detect a higher voltage across the

low side.

CONFIGURATION

The CONF pin manages the cross-conduction between

the internal MOSFET and the external low side MOSFET.

With the CONF pin at 0 V, the two MOSFETs can be

independently controlled. A load can be placed between the

high side and the low side.

With the CONF pin at 5.0 V, the two MOSFETs cannot be

on at the same time. They are in half-bridge configuration as

shown in the 33981 Simplified Application Diagram. If INHS

and INLS are at 5.0 V at the same time, INHS has priority and

OUT will be at VPWR. If INHS changes from 5.0 V to 0 V with

INLS at 5.0 V, GLS will go to high state as soon as the VGS

of the internal MOSFET is lower than 2.0 V typically. A half-

bridge application could consist in sending PWM signal to the

INHS pin and 5.0 V to the INLS pin with the CONF pin at

5.0 V.

Figure 20, illustrates the simplified application diagram in

the 33981 Simplified Application Diagram with a DC motor

and external low side. The CONF and INLS pins are at 5.0 V.

When INHS is at 5.0 V, current is flowing in the motor. When

INHS goes to 0 V, the load current recirculates in the external

low side.

BOOTSTRAP SUPPLY

Bootstrap supply provides current to charge the bootstrap

capacitor through the VPWR pin. A short time is required after

the application of power to the device to charge the bootstrap

capacitor. A typical value for this capacitor is 100 nF. An

internal charge pump allows continuous MOSFET drive.

When the device is in the sleep mode, this bootstrap supply

is off to minimize current consumption.

HIGH SIDE GATE DRIVER

The high side gate driver switches the bootstrap capacitor

voltage to the gate of the MOSFET. The driver circuit has a

low-impedance drive to ensure that the MOSFET remains

OFF in the presence of fast falling dV/dt transients on the

OUT pin.

This bootstrap capacitor connected between the power

supply and the CBOOT pin provides the high pulse current to

drive the device. The voltage across this capacitor is limited

to about 13 V typical.

An external capacitor connected between pins SR and

GND is used to control the slew rate at the OUT pin. Figure 9

and Figure 10 give VOUT rise and fall time versus different SR

capacitors.

LOW SIDE GATE DRIVER

The low side control circuitry is PWM capable. It can drive

a standard MOSFET with an RDS(ON) as low as 10.0 m at a

frequency up to 60 kHz. The VGS is internally clamped at

12 V typically to protect the gate of the MOSFET. The GLS

pin is protected against short by a local over-temperature

sensor.

THERMAL FEEDBACK

The 33981 has an analog feedback output (TEMP pin) that

provides a value in inverse proportion to the temperature of

the GND flag (pin 13). The controlling microcontroller can

“read” the temperature proportional voltage with its analog-

to-digital converter (ADC). This can be used to provide real-

time monitoring of the PC board temperature to optimize the

motor speed and to protect the whole electronic system.

TEMP pin value is VTFEED with a negative temperature

coefficient of DTFEED.

REVERSE BATTERY

The 33981 survives the application of reverse battery

voltage as low as -16 V. Under these conditions, the output’s

gate is enhanced to decrease device power dissipation. No

additional passive components are required. The 33981

survives these conditions until the maximum junction rating is

reached.

In the case of reverse battery in a half-bridge application,

a direct current passes through the external freewheeling

diode and the internal high side.

As Figure 11 shows, it is essential to protect this power

line. The proposed solution is an external N-channel low side

with its gate tied to battery voltage through a resistor. A high

side in the VPWR line could be another solution.

Analog Integrated Circuit Device Data

Freescale Semiconductor

33981

17

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