MC68060RC50 查看數據表（PDF） - Freescale Semiconductor

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MC68060RC50

M68060 User’s Manual

Freescale Semiconductor 

Table of Contents

2.3.6

2.3.7

2.3.8

2.3.9

2.3.10

2.4

2.4.1

2.4.2

2.4.3

2.5

2.5.1

2.5.2

2.5.3

2.5.4

2.5.5

2.6

2.7

2.7.1

2.7.2

2.7.3

2.7.4

2.7.5

2.8

2.8.1

2.8.2

2.8.3

2.8.4

2.9

2.9.1

2.9.2

2.9.3

2.10

2.10.1

2.10.2

2.10.3

2.11

2.11.1

2.11.2

2.11.3

2.11.4

2.11.5

2.11.6

2.12

2.13

2.14

Transfer Size (SIZ1, SIZ0).......................................................................... 2-6

Bus Lock (LOCK)........................................................................................ 2-6

Bus Lock End (LOCKE).............................................................................. 2-6

Cache Inhibit Out (CIOUT) ......................................................................... 2-7

Byte Select Lines (BS3–BS0)..................................................................... 2-7

Master Transfer Control Signals ................................................................... 2-7

Transfer Start (TS)...................................................................................... 2-8

Transfer in Progress (TIP) .......................................................................... 2-8

Starting Termination Acknowledge Signal Sampling (SAS) ....................... 2-8

Slave Transfer Control Signals ..................................................................... 2-8

Transfer Acknowledge (TA)........................................................................ 2-8

Transfer Retry Acknowledge (TRA)............................................................ 2-8

Transfer Error Acknowledge (TEA) ............................................................ 2-9

Transfer Burst Inhibit (TBI) ......................................................................... 2-9

Transfer Cache Inhibit (TCI) ....................................................................... 2-9

Snoop Control (SNOOP) .............................................................................. 2-9

Arbitration Signals....................................................................................... 2-10

Bus Request (BR)..................................................................................... 2-10

Bus Grant (BG)......................................................................................... 2-10

Bus Grant Relinquish Control (BGR)........................................................ 2-10

Bus Tenure Termination (BTT)................................................................. 2-10

Bus Busy (BB) .......................................................................................... 2-11

Processor Control Signals .......................................................................... 2-11

Cache Disable (CDIS) .............................................................................. 2-11

MMU Disable (MDIS)................................................................................ 2-12

Reset In (RSTI)......................................................................................... 2-12

Reset Out (RSTO) .................................................................................... 2-12

Interrupt Control Signals ............................................................................. 2-12

Interrupt Priority Level (IPL2–IPL0) .......................................................... 2-12

Interrupt Pending Status (IPEND) ............................................................ 2-12

Autovector (AVEC) ................................................................................... 2-13

Status and Clock Signals............................................................................ 2-13

Processor Status (PST4–PST0)............................................................... 2-13

MC68060 Processor Clock (CLK) ............................................................ 2-14

Clock Enable (CLKEN) ............................................................................. 2-14

Test Signals ................................................................................................ 2-15

JTAG Enable (JTAG)................................................................................ 2-15

Test Clock (TCK) ...................................................................................... 2-15

Test Mode Select (TMS)........................................................................... 2-15

Test Data In (TDI)..................................................................................... 2-16

Test Data Out (TDO) ................................................................................ 2-16

Test Reset (TRST) ................................................................................... 2-16

Thermal Sensing Pins (THERM1, THERM0).............................................. 2-16

Power Supply Connections......................................................................... 2-16

Signal Summary ......................................................................................... 2-16

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M68060 USER’S MANUAL

MOTOROLA

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