SC667201MMG1 查看數據表（PDF） - Freescale Semiconductor

零件编号

产品描述 (功能)

生产厂家

SC667201MMG1

Qorivva MPC5642A Microcontroller Data Sheet

Freescale Semiconductor 

• 3 channels’ internal timebases sharable between channels

• 1 timebase from eTPU2 can be imported and used by the channels

• Global enable feature for all eMIOS and eTPU timebases

• Dedicated pin for each channel (not available on all package types)

• Each channel (0–23) supports the following functions:

— General Purpose Input/Output (GPIO)

— Single Action Input Capture (SAIC)

— Single Action Output Compare (SAOC)

— Output Pulse Width Modulation Buffered (OPWMB)

— Input Period Measurement (IPM)

— Input Pulse Width Measurement (IPWM)

— Double Action Output Compare (DOAC)

— Modulus Counter Buffered (MCB)

— Output Pulse Width & Frequency Modulation Buffered (OPWFMB)

• Each channel has its own pin (not available on all package types)

Introduction

1.5.12 Second generation enhanced time processing unit (eTPU2)

The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel with the host CPU, the eTPU2

processes instructions and real-time input events, performs output waveform generation, and accesses shared data without host

intervention. Consequently, for each timer event, the host CPU setup and service times are minimized or eliminated. A powerful

timer subsystem is formed by combining the eTPU2 with its own instruction and data RAM. High-level assembler/compiler

and documentation allows customers to develop their own functions on the eTPU2.

MPC5642A devices feature the second generation of the eTPU, called eTPU2. Enhancements of the eTPU2 over the standard

eTPU include:

• The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input

[TCRCLK]) now have an option to run at full system clock speed or system clock / 2.

• Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this

enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode.

• A new User Programmable Channel Mode has been added: the blocking, enabling, service request and capture

characteristics of this channel mode can be programmed via microcode.

• Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can

also be requested simultaneously at the same instruction.

• Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point.

• Channel digital filters can be bypassed.

The eTPU2 includes these distinctive features:

• 32 channels; each channel associated with one input and one output signal

— Enhanced input digital filters on the input pins for improved noise immunity

— Identical, orthogonal channels: each channel can perform any time function. Each time function can be assigned

to more than one channel at a given time, so each signal can have any functionality.

— Each channel has an event mechanism which supports single and double action functionality in various

combinations. It includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and

equal-only comparators.

— Input and output signal states visible from the host

• 2 independent 24-bit time bases for channel synchronization:

— First time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), or by

output of second time base prescaler

MPC5642A Microcontroller Data Sheet, Rev. 3.1

Freescale Semiconductor

15

Share Link: