SC667201MMG1 查看數據表（PDF） - Freescale Semiconductor
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SC667201MMG1 Datasheet PDF : 120 Pages
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Introduction
1.5.14 Enhanced queued analog-to-digital converter (eQADC)
The eQADC block provides accurate and fast conversions for a wide range of applications. The eQADC provides a parallel
interface to two on-chip analog-to-digital converters (ADC), and a single master to single slave serial interface to an off-chip
external device. Both on-chip ADCs have access to all the analog channels.
The eQADC prioritizes and transfers commands from six command conversion command ‘queues’ to the on-chip ADCs or to
the external device. The block can also receive data from the on-chip ADCs or from an off-chip external device into the six
result queues, in parallel, independently of the command queues. The six command queues are prioritized with Queue_0 having
the highest priority and Queue_5 the lowest. Queue_0 also has the added ability to bypass all buffering and queuing and abort
a currently running conversion on either ADC and start a Queue_0 conversion. This means that Queue_0 will always have a
deterministic time from trigger to start of conversion, irrespective of what tasks the ADCs were performing when the trigger
occurred. The eQADC supports software and external hardware triggers from other blocks to initiate transfers of commands
from the queues to the on-chip ADCs or to the external device. It also monitors the fullness of command queues and result
queues, and accordingly generates DMA or interrupt requests to control data movement between the queues and the system
memory, which is external to the eQADC.
The ADCs also support features designed to allow the direct connection of high impedance acoustic sensors that might be used
in a system for detecting engine knock. These features include differential inputs; integrated variable gain amplifiers for
increasing the dynamic range; programmable pull-up and pull-down resistors for biasing and sensor diagnostics.
The eQADC also integrates a programmable decimation filter capable of taking in ADC conversion results at a high rate,
passing them through a hardware low pass filter, then down-sampling the output of the filter and feeding the lower sample rate
results to the result FIFOs. This allows the ADCs to sample the sensor at a rate high enough to avoid aliasing of out-of-band
noise; while providing a reduced sample rate output to minimize the amount DSP processing bandwidth required to fully
process the digitized waveform.
The eQADC provides the following features:
• Dual on-chip ADCs
— 2 12-bit ADC resolution
— Programmable resolution for increased conversion speed (12-bit, 10-bit, 8-bit)
– 12-bit conversion time – 938 ns (1M sample/s)
– 10-bit conversion time – 813 ns (1.2M sample/s)
– 8-bit conversion time – 688 ns (1.4M sample/s)
— Up to 10-bit accuracy at 500K sample/s and 8-bit accuracy at 1M sample/s
— Differential conversions
— Single-ended signal range from 0 to 5 V
— Sample times of 2 (default), 8, 64, or 128 ADC clock cycles
— Provides time stamp information when requested
— Allows time stamp information relative to eTPU clock sources, such as an angle clock
— Parallel interface to eQADC command FIFOs (CFIFOs) and result FIFOs (RFIFOs)
— Supports both right-justified unsigned and signed formats for conversion results
• 40 single-ended input channels, expandable to 56 channels with external multiplexers (supports 4 external 8-to-1
muxes)
• 8 channels can be used as 4 pairs of differential analog input channels
• Differential channels include variable gain amplifier for improved dynamic range (1, 2, 4)
• Differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics
(200 k100 k5 k
• Additional internal channels for monitoring voltages (such as core voltage, I/O voltage, LVI voltages, etc.) inside the
device
• An internal bandgap reference to allow absolute voltage measurements
• Silicon die temperature sensor
MPC5642A Microcontroller Data Sheet, Rev. 3.1
Freescale Semiconductor
17
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