SC667201MMG1 查看數據表（PDF） - Freescale Semiconductor

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SC667201MMG1

Qorivva MPC5642A Microcontroller Data Sheet

Freescale Semiconductor 

Introduction

• Each message buffer configurable as Rx or Tx, all supporting standard and extended messages

• Includes 1088 bytes of embedded memory for message buffer storage

• Includes 256-byte memory for storing individual Rx mask registers

• Full-featured Rx FIFO with storage capacity for 6 frames and internal pointer handling

• Powerful Rx FIFO ID filtering, capable of matching incoming IDs against 8 extended, 16 standard or 32 partial (8 bits)

IDs, with individual masking capability

• Selectable backwards compatibility with previous FlexCAN versions

• Programmable clock source to the CAN Protocol Interface, either system clock or oscillator clock

• Listen only mode capability

• Programmable loop-back mode supporting self-test operation

• 3 programmable Mask Registers

• Programmable transmit-first scheme: lowest ID, lowest buffer number or highest priority

• Time Stamp based on 16-bit free-running timer

• Global network time, synchronized by a specific message

• Maskable interrupts

• Warning interrupts when the Rx and Tx Error Counters reach 96

• Independent of the transmission medium (an external transceiver is assumed)

• Multi-master concept

• High immunity to EMI

• Short latency time due to an arbitration scheme for high-priority messages

• Low power mode, with programmable wakeup on bus activity

1.5.18 FlexRay

The MPC5642A includes one dual-channel FlexRay module that implements the FlexRay Communications System Protocol

Specification, Version 2.1 Rev A. Features include:

• Single channel support

• FlexRay bus data rates of 10 Mbit/s, 8 Mbit/s, 5 Mbit/s, and 2.5 Mbit/s supported

• 128 message buffers, each configurable as:

— Receive message buffer

— Single-buffered transmit message buffer

— Double-buffered transmit message buffer (combines two single-buffered message buffers)

• 2 independent receive FIFOs

— 1 receive FIFO per channel

— Up to 255 entries for each FIFO

• ECC support

1.5.19 System timers

The system timers include two distinct types of system timer:

• Periodic interrupts/triggers using the Periodic Interrupt Timer (PIT)

• Operating system task monitors using the System Timer Module (STM)

1.5.19.1 Periodic interrupt timer (PIT)

The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. The PIT has

no external input or output pins and is intended to provide system ‘tick’ signals to the operating system, as well as periodic

MPC5642A Microcontroller Data Sheet, Rev. 3.1

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Freescale Semiconductor

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