MS81V04166 查看數據表（PDF） - Oki Electric Industry

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MS81V04166

Dual FIFO (262,214 Words ×8 Bits) × 2

Oki Electric Industry 

1Semiconductor

PEDS81V04166-01

MS81V04166

Write Cycle Timing (Write Enable): MODE1 = VSS

n cycle

Disable cycle Disable cycle

n + 1 cycle

VIH

SWCK1, 2

tWENH

tWDSH

tWDSS

tWENS

VIL

WE1, 2

tWWEL

tWWEH

DI

n

10-17/20-27

VIH

VIL

VIH

n+1

n+2

VIL

VIH

IE1, 2

VIL

VIH

RSTW1, 2

VIL

Write Cycle Timing (Input Enable): MODE1 = VSS

n cycle

n + 1 cycle

n + 2 cycle

n + 3 cycle

VIH

SWCK1, 2

tIENH

tIDSH

tIDSS

tIENS

VIL

IE1, 2

DI

n

10-17/20-27

tWIEL

tWIEH

n

VIH

VIL

VIH

n+3

n+4

VIL

VIH

WE1, 2

VIL

VIH

RSTW1, 2

VIL

15/19

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