NJU26123V 查看數據表（PDF） - Japan Radio Corporation

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NJU26123V

Digital Signal Processor for TV

Japan Radio Corporation  

NJU26123

3. Digital Audio Interface

3.1 Digital Audio Data Format

The NJU26123 can use three kinds of formats hereafter as industry-standard digital audio data format.

(1) I2S

: MSB is put on the 2nd bit of LR clock change rate.(1 bit is delayed to left stuffing)

(2) Left-justified : LR clock -- MSB is placed for changing.

(3) Right-justified : LSB is placed just before LR clock change rate.

The main differences among three kinds of formats are in the position relation between LR clock (LR) and

an audio data (SDI, SDO).

- In every format:

: a left channel is transmitted previously.

- In Right/Left-justified : LR clock ='High' shows a left channel.

- I2S

: LR clock=”Low” shows a left channel.

- The Bit clock BCK is used as a shift clock of transmission data. The number of clocks more than

the number of sum total transmission bits of a L/R channel is needed at least.

- One cycle of LR clock is one sample of a stereo audio data. The frequency of LR clock becomes

equal to a sample rate (Fs).

- The NJU26123 supports serial data format which includes 32(32fs) or 64(64fs) BCK clocks.

This serial data format is applied to both MASTER and SLAVE mode.

3.2 Serial Audio Data Input/output

The NJU26123 audio interface includes 3 data input lines: SDI0, SDI1 and SDI2 (Table 8). 3 data output

lines: SDO0, SDO1 and SDO2. (Table 9).

Table 8 Serial Audio Input Pin Description

Pin No. Symbol

Description

6

SDI0 Audio Data Input 0 L/R

5

SDI1 Audio Data Input 1 L/R

4

SDI2 Audio Data Input 2 L/R

Table 9 Serial Audio Output Pin Description

Pin No. Symbol

Description

19

SDO0 Audio Data Output 0 L/R

20

SDO1 Audio Data Output 1 L/R

21

SDO2 Audio Data Output 2 L/R

Ver.2008-04-17

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