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PCA9538A 查看數據表(PDF) - NXP Semiconductors.

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PCA9538A Datasheet PDF : 37 Pages
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NXP Semiconductors
PCA9538A
Low-voltage 8-bit I2C-bus I/O port with interrupt and reset
8.3 Power-on reset requirements
In the event of a glitch or data corruption, PCA9538A can be reset to its default conditions
by using the power-on reset feature. Power-on reset requires that the device go through a
power cycle to be completely reset. This reset also happens when the device is
powered on for the first time in an application.
The two types of power-on reset are shown in Figure 15 and Figure 16.
VDD
ramp-up
ramp-down
td(rst)
re-ramp-up
(dV/dt)r
(dV/dt)f
time to re-ramp
when VDD drops
below 0.2 V or to VSS
(dV/dt)r
Fig 15. VDD is lowered below 0.2 V or 0 V and then ramped up to VDD
time
002aah329
VDD
ramp-down
ramp-up
VI drops below POR levels
(dV/dt)f
td(rst)
time to re-ramp
when VDD drops
to VPOR(min) − 50 mV
(dV/dt)r
time
002aah330
Fig 16. VDD is lowered below the POR threshold, then ramped back up to VDD
Table 10 specifies the performance of the power-on reset feature for PCA9538A for both
types of power-on reset.
Table 10. Recommended supply sequencing and ramp rates
Tamb = 25 C (unless otherwise noted). Not tested; specified by design.
Symbol Parameter
Condition
Min Typ Max Unit
(dV/dt)f fall rate of change of voltage
Figure 15
0.1 -
2000 ms
(dV/dt)r
td(rst)
rise rate of change of voltage
reset delay time
VDD(gl)
tw(gl)VDD
glitch supply voltage difference
supply voltage glitch pulse width
Figure 15
0.1 -
Figure 15; re-ramp time when
VDD drops to VSS
1
-
Figure 16; re-ramp time when
VDD drops to VPOR(min) 50 mV
1
-
Figure 17
[1] -
-
Figure 17
[2] -
-
2000 ms
-
s
-
s
1.0 V
10
s
VPOR(trip) power-on reset trip voltage
falling VDD
rising VDD
0.7 -
-
-
-
V
1.4 V
[1] Level that VDD can glitch down to, but not cause a functional disruption when tw(gl)VDD < 1 s.
[2] Glitch width that will not cause a functional disruption when VDD(gl) = 0.5 VDD.
PCA9538A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 28 September 2012
© NXP B.V. 2012. All rights reserved.
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