PCA9539BS 查看數據表（PDF） - NXP Semiconductors.
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PCA9539BS Datasheet PDF : 31 Pages
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NXP Semiconductors
PCA9539; PCA9539R
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.6.2 Reading the port registers
In order to read data from the PCA9539; PCA9539R, the bus master must first send the
PCA9539; PCA9539R address with the least significant bit set to a logic 0 (see Figure 5
“PCA9539; PCA9539R device address”). The command byte is sent after the address and
determines which register will be accessed. After a restart, the device address is sent
again, but this time the least significant bit is set to a logic 1. Data from the register
defined by the command byte will then be sent by the PCA9539; PCA9539R (see
Figure 9, Figure 10 and Figure 11). Data is clocked into the register on the falling edge of
the acknowledge clock pulse. After the first byte is read, additional bytes may be read but
the data will now reflect the information in the other register in the pair. For example, if you
read Input port 1, then the next byte read would be Input port 0. There is no limitation on
the number of data bytes received in one read transmission but the final byte received, the
bus master must not acknowledge the data.
slave address
SDA S 1 1 1 0 1 A1 A0 0 A
COMMAND BYTE
A (cont.)
START condition
R/W
acknowledge
from slave
slave address
acknowledge
from slave
data from lower or
upper byte of register
MSB
LSB
(cont.) S 1 1 1 0 1 A1 A0 1 A
DATA (first byte)
A
data from upper or
lower byte of register
MSB
LSB
DATA (last byte)
NA P
(repeated)
START condition
R/W
acknowledge
from slave
acknowledge
from master
no acknowledge STOP
from master condition
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
002aad727
Remark: Transfer can be stopped at any time by a STOP condition.
Fig 9. Read from register
PCA9539_PCA9539R_5
Product data sheet
Rev. 05 — 28 July 2008
© NXP B.V. 2008. All rights reserved.
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