LTC1196 查看數據表（PDF） - Linear Technology

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LTC1196

8-Bit, SO-8, 1Msps ADCs with Auto-Shutdown Options

Linear Technology 

LTC1196/LTC1198

APPLICATIONS INFORMATION

“–” Input Settling

At the end of the tSMPL, the input capacitor switches to the

“–” input and conversion starts (see Figures 1 and 7). During

the conversion, the “+” input voltage is effectively “held”

by the sample-and-hold and will not affect the conversion

result. However, it is critical that the “–” input voltage settle

completely during the first CLK cycle of the conversion time

and be free of noise. Minimizing RSOURCE– will improve

settling time. If a large “–” input source resistance must

be used, the time allowed for settling can be extended by

using a slower CLK frequency.

Input Op Amps

When driving the analog inputs with an op amp it is im-

portant that the op amp settle within the allowed time (see

Figures 1 and 7). Again, the “+” and “–” input sampling

times can be extended as described above to accommodate

slower op amps.

To achieve the full sampling rate, the analog input should

be driven with a low impedance source (<100Ω) or a

high speed op amp (e.g., the LT1223, LT1191 or LT1226).

Higher impedance sources or slower op amps can easily

be accommodated by allowing more time for the analog

input to settle as described above.

Source Resistance

The analog inputs of the LTC1196/LTC1198 look like a 25pF

capacitor (CIN) in series with a 120Ω resistor (RON) as

shown in Figure 8. CIN gets switched between the selected

“+” and “–” inputs once during each conversion cycle.

Large external source resistors will slow the settling of the

inputs. It is important that the overall RC time constants

be short enough to allow the analog inputs to completely

settle within tSMPL.

“+”

RSOURCE+ INPUT

VIN+

“–”

VIN–

RSOURCE– INPUT

ltSMPL RON

120Ω

tSMPLn

LTC1196

LTC1198

CIN

25pF

1196/98 F08

Figure 8. Analog Input Equivalent Circuit

REFERENCE INPUT

The voltage on the reference input of the LTC1196 defines

the voltage span of the A/D converter. The reference input

has transient capacitive switching currents which are due to

the switched-capacitor conversion technique (see Figure 9).

During each bit test of the conversion (every CLK cycle), a

capacitive current spike will be generated on the reference

pin by the ADC. These high frequency current spikes will

settle quickly and do not cause a problem if the reference

input is bypassed with at least a 0.1μF capacitor.

The reference input can be driven with standard volt-

age references. Bypassing the reference with a 0.1μF

capacitor is recommended to keep the high frequency

impedance low as described above. Some references

require a small resistor in series with the bypass capaci-

tor for frequency stability. See the individual reference

data sheet for details.

ROUT

REF+

5

LTC1196

EVERY CLK CYCLE

VREF

GND

4

RON

5pF TO

30pF

1196/98 F09

Figure 9. Reference Input Equivalent Circuit

Reduced Reference Operation

The minimum reference voltage of the LTC1198 is limited

to 2.7V because the VCC supply and reference are internally

tied together. However, the LTC1196 can operate with

reference voltages below 1V.

The effective resolution of the LTC1196 can be increased

by reducing the input span of the converter. The LTC1196

exhibits good linearity and gain over a wide range of ref-

erence voltages (see typical curves of Linearity and Full-

Scale Error vs Reference Voltage). However, care must be

taken when operating at low values of VREF because of the

reduced LSB step size and the resulting higher accuracy

requirement placed on the converter. The following factors

must be considered when operating at low VREF values.

1. Offset

2. Noise

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