PSD813F1-A 查看數據表（PDF） - STMicroelectronics

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PSD813F1-A

Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs

STMicroelectronics 

PSD813F1-A

PSD813F1

Architectural

Overview

(cont.)

Preliminary

5.7 In-System Programming

Using the JTAG signals on Port C, the entire PSD813F1 device can be programmed or

erased without the use of the microcontroller. The main Flash memory can also be

programmed in-system by the microcontroller executing the programming algorithms out

of the EEPROM or SRAM. The EEPROM can be programmed the same way by executing

out of the main Flash memory. The PLD logic or other PSD813F1 configuration can be

programmed through the JTAG port or a device programmer. Table 4 indicates which

programming methods can program different functional blocks of the PSD813F1.

Table 4. Methods of Programming Different Functional Blocks of the PSD813F1

Functional Block

JTAG

Device In-System Parallel

Programming Programmer Programming

Main Flash memory

Yes

Yes

Yes

EEPROM memory

Yes

Yes

Yes

PLD Array (DPLD and CPLD)

Yes

Yes

No

PSD Configuration

Yes

Yes

No

Optional OTP Row

No

Yes

Yes

5.8 Power Management Unit

The Power Management Unit (PMU) in the PSD813F1 gives the user control of the

power consumption on selected functional blocks based on system requirements. The PMU

includes an Automatic Power Down unit (APD) that will turn off device functions due to

microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce power

consumption.

The PSD813F1 also has some bits that are configured at run-time by the MCU to reduce

power consumption of the CPLD. The turbo bit in the PMMR0 register can be turned off and

the CPLD will latch its outputs and go to sleep until the next transition on its inputs.

Additionally, bits in the PMMR2 register can be set by the MCU to block signals from

entering the CPLD to reduce power consumption. See section 9.5.

8

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