S3C72B9 查看數據表（PDF） - Samsung
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S3C72B9 Datasheet PDF : 37 Pages
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S3C72B5/C72B7/C72B9/P72B9
PRODUCT OVERVIEW
Table 1-1. S3C72B5/C72B7/C72B9 Pin Descriptions (Continued)
Pin Name
INT0
INT1
INT2
INT4
M
LCDFR
CLO1
CLO2
CL
TCLO0
TCLO1
TCL0
TCL1
CIN0–CIN2
SEG0–SEG47
SEG48–
SEG79
SEG80–
SEG87
COM0–COM7
COM8–COM15
Pin Type
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
Description
External interrupts with rising/falling edge detection
External interrupts with rising/falling edge detection
External quasi-interrupts with rising/falling edge
detection
External interrupts with rising/falling edge detection
Alternated signal for SEG driver
Synchronous frame signal for SEG driver
Clock output or operating clock for SEG driver
Clock output or operating clock for SEG driver
Data shift clock for SEG driver
Timer/counter0 clock output
Timer/counter1 clock output
External clock input for timer/counter 0
External clock input for timer/counter 1
CIN0,1: comparator input only
CIN2: comparator input or external reference input
LCD segment data output
LCD segment data output
LCD segment data output
LCD common data output
LCD common data output
VLC1–VLC5
VDD
VSS
Xin, Xout
XTin, XTout
TEST
RESET
–
LCD power supply. Voltage dividing resistors are
fixed.
–
Main power supply
–
Ground
–
Crystal, Ceramic, or RC oscillator signal I/O for main
system clock.
–
Crystal oscillator signal I/O for subsystem clock.
I
Test signal input (must be connected to VSS)
I
Reset signal
Number
28
29
30
31
32
33
34
35
36
36
37
38
39
40, 41
42
122–75
74–43
2,1,
128–123
10–3
123–128
1, 2
15–11
20
21
23, 22
25, 26
24
27
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
Share Pin
P1.0
P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P2.3
P3.0
P3.0
P3.1
P3.2
P3.3
P4.0–P4.1
P4.2
–
Port13–6
COM15–8
–
SEG87–80
–
–
–
–
–
–
–
1-11
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