SPCA701A 查看數據表（PDF） - Unspecified

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SPCA701A

DIGITAL VIDEO ENCODER FOR VIDEOCD

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Preliminary

SPCA701A

Table 3. Configuration Register Settings

Mode Register

Name

set to 0

EFIELD

The VSYNC pin will output

normal vertical

synchronization signal.

PAL625

525-line operation will be

select

YCSWAP

Do not swap Y and Cr/Cb

Set to 1

The VSYNC pin will output field

signal. Low at VSYNC pin for

even field, high for odd field

The 625-line operation will be

select

Swap Y and Cr/Cb sequence

Comments

This is only used at

master mode.

This is only used at

master mode

----

CLOCK TIMING

A clock signal with a frequency twice the luminance sampling rate must be present at the CLK pin. All setup and

hold timing specifications are measured with respect to the rising edge of this signal.

PIXEL INPUT TIMING

PIXEL SEQUENCE

Multiplexed Y, Cb, and Cr data is input through the DATA[7:0] inputs. By default, the input sequence for active

video pixels must be Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3, etc., in accordance with CCIR-656. This pattern

begins during the first CLK period after the falling edge of HSYNC* (regardless of the setting of SLAVE/MASTER

mode). The order of Cb and Cr can be reversed by setting the CBSWAP pin. Figure 1 illustrates the timing.

If the pixel stream input to the SPCA701A is off by one CLK period, the SPCA701A can lock to the pixel stream

by setting the YCSWAP register. This would solve the problem of having the Y and Cr/Cb pixels swapped.

Figure 1. Pix Sequence

CBSWAP(1)

CLK(2)

HSYNC*(3)

0

P[7:0]

Cbn

Yn

Crn

Yn + 1

Cbn+2

1

P[7:0]

Crn

Yn

Cbn

Yn + 1

Crn+2

Notes: (1). CBSWAP is pin 11.

(2). Pixel transitions must occur observing setup and hold timing about the rising edge of CLK.

(3). Pixel sequence will beging with Cbn at 4 x m clock periods following the falling edge of HSYNC*, when m

is an integer.

Sunplus Technology Co., Ltd.

4

Rev.: 0.2 1999.12.07

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