STK16CA8 查看數據表（PDF） - Simtek Corporation
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STK16CA8 Datasheet PDF : 12 Pages
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STK16CA8
DEVICE OPERATION
The STK16CA8 has two separate modes of opera-
tion: SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as a standard fast
static RAM. In nonvolatile mode, data is transferred
from SRAM to the nonvolatile elements (the STORE
operation) or from the nonvolatile elements to SRAM
(the RECALL operation). In this mode SRAM func-
tions are disabled.
SRAM READ
The STK16CA8 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A0-16 determines which of the 131,072 data
bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of tAVQV (READ cycle #1). If the READ is
initiated by E or G, the outputs will be valid at tELQV or
at tGLQV, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address changes
within the tAVQV access time without the need for tran-
sitions on any control input pins, and will remain valid
until new output data appears or until E or G is
brought high, or W is brought low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
AutoStorePlus™ OPERATION
The STK16CA8’s automatic STORE on power-down
is completely transparent to the system. The
AutoStore™ initiation takes less than 500ns when
power is lost (VCC < VSWITCH) at which point the part
depends only on its internal capacitor for STORE
completion.
In order to prevent unneeded STORE operations,
automatic STOREs will be ignored unless at least
one WRITE operation has taken place since the most
recent STORE or RECALL cycle. Software initiated
STORE cycles are performed regardless of whether
or not a WRITE operation has taken place.
POWER-UP RECALL
During power up, or after any low-power condition
(VCCX < VSWITCH), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK16CA8 is in a WRITE state at the end of
power-up RECALL, the WRITE will be inhibited and E
or W must be brought high and then low for a write
to initiate.
SOFTWARE NONVOLATILE STORE
The STK16CA8 software STORE cycle is initiated by
executing sequential E controlled READ cycles from
six specific address locations. During the STORE
cycle an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvol-
atile elements. The program operation copies the
SRAM data into nonvolatile memory. Once a STORE
cycle is initiated, further input and output are dis-
abled until the cycle is completed.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence, or the sequence will be
aborted and no STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
4E38 (hex)
B1C7 (hex)
83E0 (hex)
7C1F (hex)
703F (hex)
8FC0 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
The software sequence must be clocked with E con-
trolled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence, and
it is necessary that G be low for the sequence to be
September 2003
8 Document Control # ML0023 rev 0.1
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