STP08CDC596 查看數據表（PDF） - STMicroelectronics

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STP08CDC596

8-Bit constant current Led sink driver with full outputs detection

STMicroelectronics 

STP08CDC596

7

Timing diagram

Figure 7. Timing diagram

Timing diagram

OObbssoolleettee PPrroodduucctt((ss)) -- OObbssoolleettee PPrroodduucctt((ss)) Note:

In normal mode the OE/DM2 must remain low at least two clock cycles. In case of OE signal

enabled (OE = LOW) during no clock activity (clock stopped), after the CLK restarts, 3 full

CLK cycles are necessary before disabling the OE signal (OE = High).

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