UPSD3253B-40 查看數據表（PDF） - STMicroelectronics
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UPSD3253B-40
STMicroelectronics
UPSD3253B-40 Datasheet PDF : 176 Pages
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µPSD325X DEVICES
Figure 82. Input Macrocell Timing (product term clock)
tINH
tINL
PT CLOCK
tIS
tIH
INPUT
OUTPUT
AI03101
tINO
Table 127. Input Macrocell Timing (5V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Unit
tIS
Input Setup Time
(Note 1)
0
ns
tIH
Input Hold Time
(Note 1)
15
+ 10 ns
tINH
NIB Input High Time
(Note 1)
9
ns
tINL
NIB Input Low Time
(Note 1)
9
ns
tINO
NIB Input to Combinatorial Delay
(Note 1)
34
+ 2 + 10 ns
Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX.
Table 128. Input Macrocell Timing (3V Devices)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Unit
tIS
Input Setup Time
(Note 1)
0
ns
tIH
Input Hold Time
(Note 1)
25
+ 20 ns
tINH
NIB Input High Time
(Note 1)
12
ns
tINL
NIB Input Low Time
(Note 1)
12
ns
tINO
NIB Input to Combinatorial Delay
(Note 1)
46
+ 4 + 20 ns
Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX.
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