UPSD3253B-40 查看數據表（PDF） - STMicroelectronics

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UPSD3253B-40

Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM

STMicroelectronics 

µPSD325X DEVICES

Figure 83. Peripheral I/O READ Timing

ALE

A/D BUS

CSI

RD

ADDRESS

tAVQV (PA)

tSLQV (PA)

tRLQV (PA)

DATA VALID

tRHQZ (PA)

tDVQV (PA)

DATA ON PORT A

Table 131. Port A Peripheral Data Mode READ Timing (5V Devices)

Symbol

Parameter

Conditions

Min

tAVQV–PA

Address Valid to Data

Valid

tSLQV–PA

CSI Valid to Data Valid

tRLQV–PA

RD to Data Valid

tDVQV–PA

Data In to Data Out Valid

tRHQZ–PA

RD to Data High-Z

Note: 1. Any input used to select Port A Data Peripheral Mode.

2. Data is already stable on Port A.

(Note 1)

(Note 2)

Table 132. Port A Peripheral Data Mode READ Timing (3V Devices)

Symbol

Parameter

Conditions

Min

tAVQV–PA

Address Valid to Data Valid

tSLQV–PA

CSI Valid to Data Valid

tRLQV–PA

RD to Data Valid

tDVQV–PA

Data In to Data Out Valid

tRHQZ–PA

RD to Data High-Z

Note: 1. Any input used to select Port A Data Peripheral Mode.

2. Data is already stable on Port A.

(Note 1)

(Note 2)

AI06610

Max

Turbo

Off

Unit

37

+ 10 ns

27

+ 10 ns

32

ns

22

ns

23

ns

Max

Turbo

Off

Unit

50

+ 20 ns

37

+ 20 ns

45

ns

38

ns

36

ns

164/176

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