VORTEX86SX 查看數據表（PDF） - Unspecified
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VORTEX86SX Datasheet PDF : 30 Pages
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AA16, AC14, Y1,
AA7
AE8
AB8
AA3, AA1, AB2,
AD2,AA2, AD3,
AB7, AE5, AC7,
AD6, AC2, AE13,
AB11, AA12, AB13
AF12, AC3
AA9, AD5, AB9
AC13
AC15, AD13, AE14,
AA15, AD15, AB15,
AE9
AF9
AE12
AF4, AF2,
AC8, AF3, AE6,
AB14,
AE7, AC1, AD7,
AD1, AE2
AE15, AF11, AA11,
Y5, AC9, AD4,
AB12
AD8
AA10
AA8
Y2
AB16
AF7, AD11, AB10,
Y3, AF13, AB3,
AD9
AF6
AF10
AF5
AE4
AE1
AE3
AF8
IOCHRDY_
AEN
SA[16:0]
SA[19:17]
SBHE_
LA[23:17]
MEMR_
MEMW_
RST_DRV
IRQ[7:3],
IRQ[12:9],
IRQ[15:14]
DRQ[7:5],
DRQ[3:0]
0WS_
SMEMR_
SMEMW_
IOW_
IOR_
DACK_[7:5],
DACK_[3:0]
REFRESH_
SYSCLK
TC
BALE
MEMCS16_
IOCS16_
OSC14M
Vortex86SX
32-Bit x86 Embedded SoC
memory or I/O write cycles.
I
ISA system ready. This input signal is used to extend the ISA command
width for the CPU and DMA cycles.
O
ISA address enable. This active high output indicates that the system
address is enabled during the DMA refresh cycles.
O
ISA slot address bus. These signals are high impedance during hold
acknowledge.
O ISA slot address bus. ISA slot address bus for 62-pin slot.
O
ISA Bus high enable. In master cycle, it is an input polarity signal and is
driven by the master device.
O ISA latched address bus. These are input signal during ISA master cycle.
O ISA memory read. This signal is an input during ISA master cycle.
O ISA memory write. This signal is an input during ISA master cycle.
O Driver Reset. This output signal is driven active during system power up.
I Interrupt request signals. These are interrupt request input signals.
I DMA device request. These are DMA request input signals.
I
ISA zero wait state. This is the ISA device zero-wait state indicator signal.
This signal terminates the CPU ISA command immediately.
O
ISA system memory read. This signal indicates that the memory read cycle
is for an address below 1M byte address.
O
ISA system memory write. This signal indicates that the memory write cycle
is for an address below 1M byte address.
O ISA I/O write. This signal is an input during ISA master cycle.
O ISA I/O read. This signal is an input during ISA master cycle.
O
DMA device acknowledge signals. These are DMA acknowledge
demultiplex select signals. Input function is for hardware setting.
Refresh cycle indicator. ISA master uses this signal to notify DRAM needs
O refresh. During the memory controller's self-acting refresh cycle, M6117D
drives this signal to the I/O channels.
O System Clock Output. This signal clocks the ISA bus.
O
DMA end of process. This is the DMA channel terminal count indicating
signal.
O
Bus address latch enable. BALE indicates the presence of a valid address
at I/O slots.
I ISA 16-bit memory device select indicator signal.
I ISA 16-bit I/O device select indicator signal.
O 14.318MHz clock out
z Chip Selection Interface (3 PINs)
PIN No.
AC16
AD16
G21
Symbol
GPCS0_
GPCS1_
ROMCS_/SPICS_
Type
Description
O ISA Bus Chip Select 0. This pin is the chip select for ISA bus.
O ISA Bus Chip Select 1. This pin is the chip select for ISA bus.
O
ROM Chip Select. This pin is used as a ROM chip select.
SPI Chip Select. This pin is used as SPI flash chip select.
Vortex86SX Brief Datasheet
11
Version 1.001
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