VSC7217UC 查看數據表（PDF） - Vitesse Semiconductor
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VSC7217UC Datasheet PDF : 36 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC7217
Multi-Gigabit Interconnect Chip
Features
• 4 ANSI X3T11 Fibre Channel and IEEE
802.3z Gigabit Ethernet Compliant Trans-
ceivers
• Over 8 Gb/s Duplex Raw Data Rate
• Redundant PECL Tx Outputs and Rx Inputs
• 8B/10B Encoder/Decoder per Channel,
Optional Encoder/Decoder Bypass Operation
• “ASIC-FriendlyTM” Timing Options for
Transmitter Parallel Input Data
• Elastic Buffers for Intra/Inter-Chip Cable
Deskewing and Channel-to-Channel Align-
ment
• Tx/Rx Rate Matching via IDLE Insertion/
Deletion
VSC7217 Block Diagram
TD(7:0)
C/DD
WSEND
TC(7:0)
C/DC
WSENC
TB(7:0)
C/DB
WSENB
TA(7:0)
C/DA
WSENA
KCHAR
TBCA
TBCB
TBCC
TBCD
DUAL
REFCLKP
REFCLKN
TRANSMITTER
8
8
DQ
PTXEND
8B/10B 10
Encode
LBTXD
LBEND(1:0)
RXP/RD
PTXD+ PRXD+
PTXD- PRXD-
RTXD+ RRXD+
RTXD- RRXD-
8
8
DQ
RTXEND
PTXENC
8B/10B 10
Encode
LBTXC
LBENC(1:0)
RXP/RC
PTXC+ PRXC+
PTXC- PRXC-
RTXC+ RRXC+
RTXC- RRXC-
8
8
DQ
RTXENC
PTXENB
8B/10B 10
Encode
LBTXB
LBENB(1:0)
RXP/RB
PTXB+ PRXB+
PTXB- PRXB-
RTXB+ RRXB+
RTXB- RRXB-
8
8
DQ
RTXENB
PTXENA
8B/10B 10
Encode
LBTXA
LBENA(1:0)
RXP/RA
PTXA+ PRXA+
PTXA- PRXA-
RTXA+ RRXA+
RTXA- RRXA-
RTXENA
4
x20/x10
Clock Gen
CAP0 CAP1
Tx Clock
REFCLK
TBERRA
TBERRB
TBERRC
TBERRD
TMODE(2:0)
RMODE(1:0)
• Compatible with VSC7211/7212/7214
• Fast-Locking CRU: 100-Bit Clock Periods
• Received Data Aligned to Local REFCLK or to
Recovered Clock
• PECL Rx Signal Detect and Cable Equalization
• Per-Channel Serial Tx-to-Rx and Parallel Rx-to-
Tx Internal Loopback Modes
• Clock Multiplier Generates Baud Rate Clock
• Automatic Lock-to-Reference
• JTAG Boundary Scan Support for TTL I/O
• Built-In Self Test
• 3.3V Supply, 3.0W Typ, 3.5W Max.
• 256-pin, 27mm BGA Package
RECEIVER
Clk/Data
Recovery
8
10 8B/10B 8 Elastic
Decode 3 Buffer
PSDETD
RSDETD
Clk/Data
Recovery
8
10 8B/10B 8 Elastic
Decode 3 Buffer
PSDETC
RSDETC
Clk/Data
Recovery
8
10 8B/10B 8 Elastic
Decode 3 Buffer
PSDETB
RSDETB
Clk/Data
Recovery
8
10 8B/10B 8 Elastic
Decode 3 Buffer
PSDETA
RSDETA
WSI
FLOCK
Channel
Align
RESETN
ENDEC
BIST
TRSTN
TMS
TTDCIK
JTAG
BouSncadnary
RD(7:0)
IDLED
KCHD
ERRD
RCLKD
RCLKDN
RC7:0)
IDLEC
KCHC
ERRC
RCLKC
RCLKCN
RB(7:0)
IDLEB
KCHB
ERRB
RCLKB
RCLKBN
RA(7:0)
IDLEA
KCHA
ERRD
RCLKA
RCLKAN
WSO
TDO
G52325-0, Rev. 3.0
6/14/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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