VSC7217 查看數據表（PDF） - Vitesse Semiconductor

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VSC7217

Multi-Gigabit Interconnect Chip

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Mutli-Gigabit Interconnect Chip

Preliminary Datasheet

VSC7217

Deserializer and Character Alignment

The retimed serial data stream is converted into 10-bit characters by the deserializer. A special 7-bit

“Comma” pattern (‘0011111xxx’ or ‘1100000xxx’) is recognized by the receiver and allows it to identify the

10-bit character boundary. Note that this pattern is found in three special characters: K28.1, K28.5 and K28.7.

However, K28.5 is chosen as the unique IDLE character. Only K28.1 and K28.5 should be used in normal oper-

ation. The K28.7 character should be reserved for test and characterization use.

Character alignment occurs when the deserializer synchronizes the 10-bit character framing boundary to a

“Comma” pattern in the incoming serial data stream. If the receiver identifies a “Comma” pattern in the incom-

ing data stream, which is misaligned to the current framing boundary, the receiver will re-synchronize the

recovered data in order to align the data to the new “Comma” pattern. Re-synchronization ensures that the

“Comma” character is output on the internal 10-bit bus so that bits 0 through 9 equal ‘0011111xxx’ or

‘1100000xxx’. If the “Comma” pattern is aligned with the current framing boundary, re-synchronization will

not change the current alignment. Re-synchronization is always enabled and cannot be turned off when

ENDEC is HIGH. After character re-synchronization the VSC7217 ensures that within a link, the 8-bit data

sent to the transmitting VSC7217 will be recovered by the receiving VSC7217 in the same bit locations as the

transmitter (e.g., Tn(7:0) = Rn(7:0)). When ENDEC is LOW, “Comma” detection and alignment are enabled

only if KCHAR is HIGH.

10B/8B Decoder

The 10-bit character from the deserializer is decoded in the 10B/8B decoder, which outputs the 8B data

byte and three bits of status information. If the 10-bit character does not match any valid value, an Out-of-Band

Error is generated which is output on the receiver status bus. Similarly, if the running disparity of the character

does not match the expected value, a Disparity Error is generated. The decoder also reports when a K-character

is received, and distinguishes the K28.5 (IDLE) character from other K-characters. This status information is

combined with LOS State Machine status and FIFO error status, to produce the prioritized per-character link

status output information (see Table 7).

Elastic Buffer and Channel Deskewing

An elastic buffer is included in each of the four receive channels. Decoded data and status information is

written into these buffers on each channel’s recovered clock, and is read on the selected output clock. In addi-

tion to allowing decoded data to easily cross from a channel’s recovered clock domain to its output clock

domain, the elastic buffers facilitate channel alignment (the reconstruction of a multi-byte word as presented to

the transmitting devices). In addition, the buffers facilitate rate matching via IDLE character insertion/deletion

when the channel’s recovered clock is not frequency locked to its output clock.

There are three conditions under which a receive channel’s elastic buffer is recentered: (1) the RESETN

input, when asserted, recenters the read/write pointers in each elasticity buffer, (2) whenever a Comma charac-

ter is received which changes the receive character’s framing boundary, and (3) whenever the receiver detects

the synchronization point in the Word Sync Sequence. All three of these events are associated with chip initial-

ization or link initialization and will not occur during normal data transfer. Note: recentering can result in the

loss or duplication of decoded character data and status information.

When a condition change transmit timing (phase shifts in TBC) or shifts phase/alignment into the receiver,

the user should initial a Word Sync Event to recenter all elasticity buffers. Otherwise, data corruption could

occur.

Page 8

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52325-0, Rev. 3.0

6/14/00

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