VSC8113QB1 查看數據表（PDF） - Vitesse Semiconductor

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VSC8113QB1

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

Vitesse Semiconductor 

Data Sheet

VSC8113

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Table 4: Transmit Data Input Timing Table (STS-12 Operation)

Parameter

Description

Min

TCLKIN

Transmit data input byte clock period

-

TINSU

Transmit data setup time with respect to TXLSCKIN

1.0

TINH

Transmit data hold time with respect to TXLSCKIN

1.0

TPROP

Maximum allowable propagation delay for connecting

TXLSCKOUT to TXLSCKIN

-

Typ

12.86

-

-

-

Table 5: Transmit Data Input Timing Table (STS-3 Operation)

Parameter

Description

TCLKIN

TINSU

TINH

TPROP

Transmit data input byte clock period

Transmit data setup time with respect to TXLSCKIN

Transmit data hold time with respect to TXLSCKIN

Maximum allowable propagation delay for connecting

TXLSCKOUT to TXLSCKIN

Note: Duty cycle for TXLSCKOUT is 50% +/- 10% worst case

Min

Typ

-

51.44

1.0

-

1.0

-

-

-

Figure 10: Receive Data Output Timing Diagram

Max

-

-

-

3.5

Max

-

-

-

30

Units

ns

ns

ns

ns

Units

ns

ns

ns

ns

RXCLKIN+

RXCLKIN-

RXLSCKOUT

TRXCLKIN

TRXLSCK

RXOUT [7:0]

A1

A2

A2

A2

A2

Table 6: Receive Data Output Timing Table (STS-12 Operation)

Parameter

Description

Min

TRXCLKIN Receive clock period

-

TRXLSCK

Receive data output byte clock period

-

TRXVALID

Time data on RXOUT [7:0] and FP is valid before and

after the rising edge of RXLSCKOUT

4.0

TPW

Pulse width of frame detection pulse FP

-

Typ

1.608

12.86

-

12.86

Max

-

-

-

-

Units

ns

ns

ns

ns

G52154-0, Rev 4.2

3/19/99

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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