VSC8114QB 查看數據表（PDF） - Vitesse Semiconductor

零件编号

产品描述 (功能)

生产厂家

VSC8114QB

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Data Sheet

VSC8114

Application Notes

Interconnecting the Byte Clocks (TXLSCKOUT and TXLSCKIN)

The byte clock (TXLSCKOUT and TXLSCKIN) on the VSC8114 has been brought off-chip to allow as

much flexibility in system-level clocking schemes as possible. Since the byte clock (TXLSCKOUT) clocks both

the VSC8114 and the UNI devices, it is important to pay close attention to the routing of this signal. The UNI

device in general is a CMOS part which can have very wide spreads in timing (1-11ns clock in to parallel data

out for the PM5355), which utilizes most of the 12.86ns period (at 78MHz), leaving little for the trace delays

and set-up times required to interconnect the 2 devices.

The VSC8114 and the UNI device should be placed as close to each other as possible to provide maximum

setup and hold time margin at the inputs of the VSC8114. Figure 12 suggests two different ways of routing the

TXLSCKOUT-to-TXLSCKIN clock trace when used in a 622 MHz mode, which ever method is used the trans-

mission line trace impedance should be no lower than 75 ohms.

Figure 12: Interconnecting the Byte Clocks

VSC8114

TXIN[7:0]

PM5355

POUT[7:0]

TXLSCKIN

(1)

TXLSCKOUT

Ttrace

(2)

TCLK

(1) TXLSCKOUT and TXLSCKIN are tied together at the pins of the VSC8114. This provides a setup and

hold time margin for the TXIN input of

• Tsu,margin = Tclk - TTCLK-POUT,max(PM5355) - Tsu,min(VSC8114) - 2xTtrace = 0.86ns - 2xTtrace

• Thold,margin = TTCLK-POUT,min(PM5355) - Thold,min(VSC8114) + 2xTtrace = 2xTtrace

(2) TXLSCKOUT is daisy chained to the UNI device and then routed back to the VSC8114 along with the

byte data. This interface provides a setup and hold time margin for the TXIN input of

• Tsu,margin = Tclk - TTCLK-POUT,max(PM5355) - Tsu,min(VSC8114) = 0.86ns

• Thold,margin = TTCLK-POUT,min(PM5355) - Thold,min(VSC8114) = 0ns

Option (2) does not provide any hold time margin, while option (1) requires the one-way trace delay (Ttrace)

to be less than 0.43ns (~3 inches).

The general recommendation is to apply option (1) and place the VSC8114 and PM5355 as close to each

other as possible. If the one-way trace delay cannot be kept less than 0.43ns with a 50pf load, daisy-chaining

(option 2) should be applied - close attention must be paid to signal routing in this case because of the lack of

hold time margin.

Page 20

© VITESSE SEMICONDUCTOR CORPORATION

G52185-0, Rev 4.0

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

11/1/99

Share Link: