VSC8140TW 查看數據表（PDF） - Vitesse Semiconductor

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VSC8140TW

2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

Data Sheet

VSC8140

Transmitter High-Speed Data and Clock Outputs

The high-speed data and clock output drivers (TXOUT and TXCLKOUT) consist of a differential pair

designed to drive a 50Ω transmission line. The transmission line should be terminated with a 100Ω resistor at

the load between true and complement outputs (see Figure 13). No connection to a termination voltage is

required. The output driver is back terminated to 50Ω on-chip, providing a snubbing of any reflections. If used

single-ended, the high-speed output driver must still be terminated differentially at the load with a 100Ω resistor

between true and complement outputs.

In order to save power, the high-speed transmit clock output (TXCLKOUT) can be powered down by con-

necting the power pins VEEP_CLK and VEE_PWRDN to the VCC supply instead of to VEE.

Figure 14: AC Termination of Low-Speed LVPECL REFCLK and LPTIMCLK Inputs

VCC

R1

ZO

CIN

R2

VEE

VCC

R1

ZO

CIN

R2

VEE

Chip Boundary

VCC = 3.3V

VEE = 0V

R1||R2 = Zo , R1 = 83Ω R2 =125Ω

VCCR2 + VEER1

R1+R2

= VBIAS

CIN TYP = 100nF

for AC operation

Reference Clock Inputs

The incoming low-speed reference clock inputs are received by differential LVPECL inputs REFCLK± .

Off-chip termination of these inputs is required (see Figure 14).

In most situations these inputs will have high transition density and little DC offset. However, in cases

where this does not hold, direct DC connection is possible. All serial clock inputs have the same circuit topol-

ogy, as shown in Figure 14. If the input signal is driven differentially and DC-coupled to the part, the mid-point

of the input signal swing should be centered about the input common-mode voltage VCM and not exceed the

maximum allowable amplitude. For single-ended, DC-coupling operations, it is recommended that the user pro-

vides an external reference voltage. The external reference should have a nominal value equivalent to the com-

mon-mode switch point of the DC-coupled signal, and can be connected to either side of the differential gate.

Page 10

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52251-0, Rev. 4.0

9/6/00

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