VSC8140TW 查看數據表（PDF） - Vitesse Semiconductor

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VSC8140TW

2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

RXIN+

RXIN-

RXCLKIN+

RXCLKIN-

EQULOOP

TXOUT+

TXOUT-

TXCLKOUT+

TXCLKOUT-

Figure 11: Equipment Loopback Data Path

DQ

0

1

0

1

1:16 Serial to

Parallel

QD

16:1 Parallel to

Serial

2.48832GHz

PLL

Figure 12: Split Loopback Datapaths

Data Sheet

VSC8140

RXOUT[15:0]

RXCLK16O

RXCLK32O

TXIN[15:0]

TXCLK16I

TXCLK16O

RXIN+

RXIN-

RXCLKIN+

RXCLKIN-

TXOUT+

TXOUT-

TXCLKOUT+

TXCLKOUT-

FACLOOP

EQULOOP

DQ

1

QD

0

1

0

0

RXOUT[15:0]

1

1:16 Serial to

Parallel

0

RXCLK16O

1

RXCLK32O

16:1 Parallel to

Serial

2.48832GHz

PLL

TXIN[15:0]

TXCLK16I

TXCLK16O

Split Loopback

Equipment and Facility Loopback modes can be enabled simultaneously. In this case, high-speed serial data

received (RXIN) and clock (RXCLKIN) are muxed through to the high-speed serial outputs (TXOUT and

TXCLKOUT). The low-speed 16-bit transmit stream (TXIN[15:0]) is muxed into the low-speed 16-bit receive

output stream (RXOUT[15:0]). See Figure 12.

Looptiming

LOOPTIM0 mode bypasses the PLL when LOOPTIM0 is asserted high. In this mode, the PLL is bypassed

using the receive high-speed clock (RXCLKIN), and the entire part is synchronously clocked from a single

external source.

Page 8

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52251-0, Rev. 4.0

9/6/00

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