VSC8166 查看數據表（PDF） - Vitesse Semiconductor
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VSC8166 Datasheet PDF : 16 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec
1:16 SONET/SDH Demux with Clock Recovery
Preliminary Datasheet
VSC8166
Functional Description
Clock Recovery:
The incoming SONET/SDH data stream is fed both to a re-timing latch and to the integrated clock recovery
unit (CRU). The CRU exceeds the SONET/SDH jitter tolerance map. A 77.76MHz reference clock (REF-
CLK+) is required for CRU operation. Off-chip termination of this input is required. For AC coupling, a bias
voltage suitable for AC coupling needs to be provided, see Figure 1 for biasing scheme. The 77.76MHz refer-
ence is used to permit the CLK16O+ to remain locked to this external reference clock in the event of data loss.
Figure 1: AC Termination of LVPECL REFCLK Input
VCC
R1
ZO
CIN
Chip Boundary
VCC = 3.3V
Split-end equivalent termination is Zo to VTerm
R1 = 125Ω, R2 = 83Ω, Zo=50Ω, VTerm= VCC-2V
R1||R2 = Zo
VCCR2 + VEER1
R1+R2
= VBias
R2
VEE
VCC
R1
ZO
CIN
R2
VEE
VEE = 0V
CIN TYP = 100 nF
for AC operation.
The VSC8166 has a TTL input LOS to force the part into a Loss of Signal state. Most optics have a TTL
output usually called “SD” (Signal Detect), based on the optical power of the incoming light stream. Depending
on the optics manufacturer, this signal is either active high or low. To accommodate polarity differences, the
internal Loss of Signal is generated when the POL and LOS inputs are of opposite states. Once active, all zeroes
“0” will be propagated downstream using the transmit clock until the optical signal is regained and LOS and
POL are in the same logic state. When LOS and POL are opposite logic states, an internal LOS is asserted and
all output data D(0:15)+ will go to zero on the next rising edge of CLK16O+.
If LOLEN is low, and the serial input data consists of 3.3us or more of continuous zeros, LOL will go high
and remain high for 100us following the restoration of valid data. If LOLEN is high, loss of data lock “OR”
3.3us of zeros will cause LOL to go high and remain high for 100us after both the return of non-zero data, and
phase locking of the Serial data and clock are obtained.
NOREF will go high asynchronously when REFCLK is lost, or when REFCLK is not locked to the internal
2.488GHZ clock. It will remain high until the condition is corrected.
Page 2
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52252-0, Rev 3.0
11/9/99
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