VSC8166 查看數據表（PDF） - Vitesse Semiconductor
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VSC8166 Datasheet PDF : 16 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8166
2.488 Gbit/sec
1:16 SONET/SDH Demux with Clock Recovery
Low Speed Interface
The demultiplexed serial stream is made available by a 16 bit differential LVPECL interface D(15:0)+ with
accompanying differential LVPECL divide by 16 clock CLK16O± and divide by 32 clock CLK32O±. The low
speed LVPECL output drivers are designed to drive a 50Ω transmission line. The transmission line can be DC
terminated with a split end termination scheme, see Figure 2, or DC terminated by 50Ω to VCC-2V on each line,
see Figure 3. At any time, the equivalent split-end termination technique can be substituted for the traditional
50Ω to VCC-2V on each line. AC coupling can be achieved by a number of methods. Figure 4 illustrates an AC
coupling method for the occasion when the downstream device provides the bias point for AC coupling. If the
downstream device were to have internal termination, the line to line 100Ω resistor may not be necessary. The
divide by 32 output can be used to provide a reference clock for the clock multiplication unit on the VSC8163.
Figure 2: Split-end DC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs
VSC8166
Split-end equivalent termination is Zo to VTerm VCC
R1 = 125Ω R2 = 83Ω, Zo=50Ω, VTerm= VCC-2V
R1
Zo
R1 downstream
Zo
R1||R2 = Zo
VCCR2 + VEER1
R1+R2
= VTerm
R2
R2
VEE
Figure 3: Traditional DC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs
VSC8166
Zo
downstream
R1 =50Ω
VCC-2V
R1 =50Ω
VCC-2V
G52252-0, Rev. 3.0
11/9/99
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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