WED2ZL361MV 查看數據表（PDF） - White Electronic Designs Corporation
零件编号
产品描述 (功能)
生产厂家
WED2ZL361MV Datasheet PDF : 12 Pages
| |||
White Electronic Designs
WED2ZL361MV
AC Characteristics
Parameter
Clock Time
Clock Access Time
Output enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
CKE Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High
Address Advance to Clock High
Chip Select Setup to Clock High
Address Hold to Clock high
CKE Hold to Clock High
Data Hold to Clock High
Write Hold to Clock High
Address Advance to Clock High
Chip Select Hold to Clock High
Symbol
TCYC
tCD
tOE
tLZC
tOH
tLZOE
tHZOE
tHZC
tCH
tCL
tAS
tCES
tDS
tWS
tADVS
tCSS
tAH
tCEH
tDH
tWH
tADVH
tCSH
166MHz
Min Max
6.0
— 3.5
— 3.5
1.5 —
1.5 —
0.0 —
— 3.0
— 3.0
2.2 —
2.2 —
1.5 —
1.5 —
1.5 —
1.5 —
1.5 —
1.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
150MHz
Min Max
6.7
— 3.8
— 3.8
1.5 —
1.5 —
0.0 —
— 3.0
— 3.0
2.5 —
2.5 —
1.5 —
1.5 —
1.5 —
1.5 —
1.5 —
1.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
133MHz
Min Max
7.5
— 4.2
— 4.2
1.5 —
1.5 —
0.0 —
— 3.5
— 3.5
3.0 —
3.0 —
1.5 —
1.5 —
1.5 —
1.5 —
1.5 —
1.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
100MHz
Min Max
10.0
— 5.0
— 5.0
1.5 —
1.5 —
0.0 —
— 3.5
— 3.5
3.0 —
3.0 —
1.5 —
1.5 —
1.5 —
1.5 —
1.5 —
1.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. All Address inputs must meet the specified setup and hold times for all rising clock
(CLK) edges when ADV# is sampled low and CEx# is sampled valid. All other
synchronous inputs must meet the specified setup and hold times whenever this
device is chip selected.
2. Chip enable must be valid at each rising edge of CLK (when ADV# is Low) to remain
enabled.
3. A write cycle is defined by WE# low having been registered into the device at ADV
Low. A Read cycle is defined by WE# High with ADV# Low. Both cases must meet
setup and hold times.
AC Test Conditions
VSS = 0V, = 0°C ≤ TA ≤ +70°C, VCC = 3.3V ± 5%; Commercial or -40°C ≤ TA ≤ +85°C, VCC = 3.3V ± 5%; Industrial
Parameter
Input Pulse Level
Input Rise and Fall Time (Measured at 20% to 80%)
Input and Output Timing Reference Levels
Output Load
Value
0 to 3.0V
1.0V/ns
1.5V
See Output Load (A)
Output Load (A)
DOUT
Zo=50Ω
RL=50Ω
30pF*
VL=1.5V
*Including Scope and Jig Capacitance
Output Load (B)
for a tLZC, tLZOE, tHZOE, and tHZC
+3.3V
DOUT
3.9 Ω
353 Ω
5pF*
June 2004
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
Share Link: 