LC72134M 查看數據表（PDF） - SANYO -> Panasonic

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LC72134M

Dual PLL Frequency Synthesizer for FM Tuner Systems

SANYO -> Panasonic 

LC72134M

Continued from preceding page.

Pin

AMIN

Pin No.

17

Type

Function

Main PLL

local oscillator

signal input

• AMIN is selected when DVS in the serial data is set to 0.

• When SNS in the serial data is set to 1:

• Input frequency: 2 to 40 MHz

• The signal is input to the swallow counter directly.

• The divisor can be set to a value in the range 272 to 65535. The set value

becomes the actual divisor.

• When SNS in the serial data is set to 0:

• Input frequency: 0.5 to 10 MHz

• The signal is input to a 12-bit programmable divider directly.

• The divisor can be set to a value in the range 5 to 4095. The set value becomes

the actual divisor.

CE

2

Chip enable

• This pin must be set high to enable serial data input (DI) or serial data output

(DO).

Equivalent circuit

DI

3

Input data

• Input for serial data transferred from the controller

CL

4

Clock

• Clock used for data synchronization for serial data input (DI) and serial data

output (DO).

DO

VDD

VSS

BO1

BO2

BO3

BO4

IO2

PDa

5

Output data

• Output for serial data transmitted to the controller. The content of the data

transmitted is determined by DOC0 through DOC2.

19

Power supply

• LC72134M power supply (VDD = 4.5 to 5.5 V)

• The power on reset circuit operates when power is first applied.

23

Ground

• LC72134M ground

6

• Output-only ports

• The output state is determined by BO1 through BO4 in the serial data.

7

8

Output ports

When the data value is 0: The output state will be the open circuit state.

When the data value is 1: The output state will be a low level.

14

• A time base signal (8 Hz) is output from BO1 when TBC in the serial data is set to

1.

16

I/O port

• Shared function I/O port

• The pin function is determined by IOC2 in the serial data.

When the data value = 0: Input port

When the data value = 1: Output port

• When specified to function as an input port:

The input pin state is reported to the controller through the DO pin.

When the input state is low: The data will be 0:

When the input state is high: The data will be 1:

• When specified to function as an output port:

The output state is determined by IO2 in the serial data.

When the data value is 0: The output state will be the open circuit state.

When the data value is 1: The output state will be a low level.

• This pin is set to input mode after a power on reset.

• PLL charge pump output

Main PLL

A high level is output when the frequency of the local oscillator signal divided by N

20

charge pump is higher than the reference frequency, and a low level is output when that

output

frequency is lower. This pin goes to the high-impedance state when the

frequencies match.

——

——

Main PLL low-

AINa

21

pass filter

• Connections for the n-channel MOS transistor to be used for the PLL active low-

AOUTa

22

amplifier

pass filter.

transistor

Continued on next page.

No. 5814-6/27

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