ADP5020(RevA) 查看數據表（PDF） - Analog Devices
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ADP5020 Datasheet PDF : 28 Pages
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ADP5020
CONTROL REGISTERS
DEVICE ADDRESS
Following a start condition, the bus master must send the address
of the slave it is accessing. The slave address for the ADP5020 is
shown in Table 10. The Bit 0 defines the operation to be per-
Table 10. Slave Address
Bit 7
Bit 6
ADR6
ADR5
0
0
Bit 5
ADR4
1
Bit 4
ADR3
0
Data Sheet
formed. When this bit is set to Logic 1, a read operation is
selected. When this bit is set to Logic 0, a write operation is
selected.
Bit 3
ADR2
1
Bit 2
ADR1
0
Bit 1
ADR0
0
Bit 0
R/W
1 or 0
REGISTER MAP
Table 11.
Address
0x00
0x01
0x02
0x03
Register Name
Revision
BUCK1_VSEL
BUCK2_LDO_VSEL
REG_CONTROL_STATUS
0x04
OPERATIONAL_CONTROL
0x05
EN_CONTROL
0x06 to
0x0F
Reserved
D7
BK1_EN
Reserved
D6
D5
MAJ[2:0]
Reserved[7:3]
BK2_VSEL[3:0]
BK2_EN LDO_EN
D4
EN_ALL
SYNC_9P6 SYNC_19P2 SYNC_
AC
Reserved[7:2]
D3
MIN[2:0]
BK1_
PGOOD
BK1_
XSHTDN
D2
D1
D0
OPT[1:0]
BK1_VSEL[2:0]
LDO_VSEL[3:0]
BK2_
LDO_
PGOOD PGOOD
FORCE_XS
BK2_
LDO_
TSD
XSHTDN XSHTDN
ENO_HIZ_
BAR
ENO_DRV
REGISTER DESCRIPTIONS
User Accessible Registers
Table 12. Revision Register, Address 0x00
Bit Bit Name
Access Default
[7:5] MAJ[2:0]
R
N/A
[4:2] MIN[2:0]
R
N/A
[1:0] OPT[1:0]
R
N/A
Description
Major revision bits. Used to electronically ID the device version.
Minor revision bits. Used to electronically ID the device version.
Option bits. Used to electronically ID the option (multiple options on same device family).
Table 13. BUCK1_VSEL Register, Address 0x01
Bit Bit Name
Access Default Description
[7:3] Reserved
N/A
N/A
Reserved.
[2:0] BK1_VSEL[2:0] R/W
Fuse
Sets the voltage output level of the Buck 1 regulator. Preloads on power-up with values
stored in fuses. Note that this value can be edited by the user in an application.
000 = 2.5 V.
001 = 2.8 V.
010 = 2.9 V.
011 = 3.0 V.
100 = 3.2 V.
101 = 3.3 V (default).
110 = 3.7 V.
111 = reserved.
Rev. A | Page 14 of 28
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