ADP5020(RevA) 查看數據表（PDF） - Analog Devices
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ADP5020 Datasheet PDF : 28 Pages
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ADP5020
Activation Waveforms
VDDx
POR
INTERNAL
POR
VUVLOR
Data Sheet
EN
I2C BUS
BUCK 1
LDO
BUCK 2
XSHTDN
VDDx
POR
INTERNAL
POR
I2C SEQUENCER EN_
REGISTERS
ALL = 1
PROGRAMMING
tREG1
POK
tREG2
POK
tREG3
POK
tXSHTDN
Figure 23. Regulators Are Activated by I2C Command
EN_
ALL = 0
EN
I2C BUS
BUCK 1
LDO
BUCK 2
I2C SEQUENCER
REGISTERS
PROGRAMMING
tREG1
POK
tREG2
POK
tREG3
POK
tXSHTDN
XSHTDN
Figure 24. Activation Command Using the EN Pin
When activated through the EN pin, the sequencer is affected
only by the I2C commands that set or clear the regulator power
good masking bits: Bit 3 (BK1_XSHTDN), Bit 2 (BK2_XSHTDN),
and Bit 1 (LDO_XSHTDN) in the OPERATIONAL_CONTROL
register (Address 0x04). See the Default Power-On Sequence with
EN Pin section for more information. The sequence order of the
regulators is factory programmed through fuses, but the delays
between the regulators (tREG1, tREG2, and tREG3) are fixed and cannot
be changed.
The EN_ALL bit (Bit 4) in the REG_CONTROL_STATUS register
(Address 0x03) has the same functionality as the EN pin. The
sequencer has an antiglitch function that allows it to ignore supply
voltage dip if glitch time is less than 50 μs (see Figure 25).
Rev. A | Page 18 of 28
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