CMX644A 查看數據表（PDF） - CML Microsystems Plc
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CMX644A Datasheet PDF : 34 Pages
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V22 and Bell 212A Modem
CMX644A
TX PSK MODE Register ($E7)
(Bit 7)
Reserved for future use. This bit should be set to ‘0’.
TXON ENAB
(Bit 6)
This bit enables or powersaves the inverted output of the line driving
amplifier (TXON). When set to ‘1’ TXON is enabled; together with TXO
these outputs provide sufficient complementary output to drive a line
even at low VDD. When set to ‘0’ the TXON output is powersaved,
reducing the total supply current for applications in which a single-ended
output is sufficient.
SCRAMB UNLOCK
(Bit 5)
When this bit is set to ‘1’ the scrambler will check for sequences of 64
consecutive ones at its output (caused by scrambler lockup) and once
detected it will invert the next input to the scrambler. When this bit is
set to ‘0’ the lock-up prevention is disabled.
SCRAMB ENABLE
(Bit 4)
When this bit is set to ‘1’ the Tx data is passed through the scrambler.
When it is set to ‘0’ the scrambler is bypassed.
EQUAL ET1 and ET0
(Bits 3 and 2)
These 2 bits control the level of equalisation applied to the transmitted
signal according to the following table:
ET1
(Bit 3)
0
0
1
1
ET0
(Bit 2)
0
1
0
1
Transmitter
Equalisation
no equalisation
Low
Medium
High
See Figures 5a and 5b for the typical equaliser responses. The
equaliser is automatically powersaved when both ET1 and ET0 are set
to '0'.
ENABLE
(Bit 1)
HI/LO BAND
(Bit 0)
When this bit is set to ‘1’ the internal output of the PSK modulator is
enabled. When it is set to ‘0’ the internal output of the PSK modulator is
set to VBIAS. Associated flags are only set when this bit is ‘1’.
This bit determines whether the transmitted PSK signal should occupy
the low channel (900Hz - 1500Hz) or the high channel (2100Hz -
2700Hz). When the bit is set to ‘0’ the low channel is selected. When it
is set to ‘1’ the high channel is selected.
© 2000 Consumer Microcircuits Limited
15
D/644A/6
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