CMX644A 查看數據表（PDF） - CML Microsystems Plc

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CMX644A

V.22 and Bell 212A Modem

CML Microsystems Plc 

V22 and Bell 212A Modem

CMX644A

RX PARITY flag

(Bit 7)

RING DETECT CHANGE

flag (Bit 6)

DETECT flag

(Bit 5)

RX DATA OVERFLOW

flag (Bit 4)

RX DATA READY flag

(Bit 3)

TX DATA UNDERFLOW

flag (Bit 2)

TX DATA READY flag

(Bit 1)

UNSCRAM MARK flag

(Bit 0)

When this bit is ‘1’ the received parity is in error. When this bit is ‘0’ the

received parity is correct.

When RING DETECT (TONES DETECT Register, Bit 6) changes state,

this bit will be set to ‘1’.

When any of the following bits - CALL PRGRSS DETECT, CARRIER

DETECT or ANSWER DETECT (TONES DETECT Register Bits 5, 4, 3)

- change state, this bit will be set to ‘1’.

If received data is not read out of the device within the 8-bit window of

RX DATA READY going high, then this bit will be set to ‘1’ to indicate an

error condition.

When a full byte of data is received and is available in the RX DATA

BYTE register, this bit will be set to ‘1’. There is then an 8-bit window

during which the RX DATA BYTE register must be read.

If data is not loaded into the TX DATA BYTE register within the 8-bit

window of TX DATA READY going high, then this bit will be set to ‘1’ to

indicate an error condition.

When the Tx data buffer is ready to receive a new byte of data, this bit

will be set to ‘1’. There is then an 8-bit window for the loading of the TX

DATA BYTE register.

When the UNSCRAM MARK DETECT bit (TONES DETECT Register

Bit 0) changes state, this bit will be set to ‘1’.

© 2000 Consumer Microcircuits Limited

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D/644A/6

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